DETAILED ACTION
This action is responsive to the following communications: the Application filed on May 30, 2024.
Claims 1-34 are pending. Claims 1, 11, 17, 23 and 29 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because all of the Figures filed on May 30, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in greyscale. Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yabe (US 20210319833).
Regarding independent claim 23, Yabe discloses a method of performing a sensing operation in a memory device [para. 118], comprising the steps of:
preparing a memory block that includes an array of memory cells arranged in a plurality of word lines [see Fig. 4C, one hundred and twenty-eight data word line layers WLL0-WLL127 for connecting to memory cells, para. 66] and in a plurality of memory holes [the non-volatile memory cells are formed along memory holes which extend through alternating conductive and dielectric layers in the stack, para. 70], the plurality of memory holes being in electrical communication with respective bit lines of a set of bit lines [see Fig. 4B, para. 61]; and
performing a read operation on a selected word line of the plurality of word lines using only a plurality of active bit lines of the set of bit lines [see Fig. 9B, in a first (even) read interval, each of first quarter bit lines B0, B2, B4, B6, B8, B10, B12 and B14 is coupled to a corresponding one of eight sense amplifiers and the selected memory cells in even memory holes 9020, 9022, 9024, 9026, 9028, 90210, 90212 and 90214 are read, para. 118] while a plurality of inactive bit lines of the set of bit lines remain inactive [see Fig. 9B, while odd bit lines B1, B3, B5, B7, B9, B11, B13 and B15 are coupled to GROUND (or some other predetermined voltage), para. 118].
Regarding claim 25, Yabe discloses the bit lines of the set of bit lines extend at least partially in parallel relationship with one another and wherein the active bit lines and inactive bit lines are arranged in alternating fashion [see Fig. 9B, para. 118].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 13 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yabe (US 20210319833) in view of Wolstenholme (US 20160284717).
Regarding independent claim 11, Yabe discloses a memory device [Fig. 2: 200, para. 39], comprising:
a memory block that includes an array of memory cells arranged in a plurality of word lines [see Fig. 4C, one hundred and twenty-eight data word line layers WLL0-WLL127 for connecting to memory cells, para. 66] and in a plurality of memory holes [the non-volatile memory cells are formed along memory holes which extend through alternating conductive and dielectric layers in the stack, para. 70], the plurality of memory holes being in electrical communication with respective bit lines of a set of bit lines [see Fig. 4B, para. 61]; and
the set of bit lines including a plurality of active bit lines that are in electrical communication with active sense amplifiers and memory cells during read operations and that extend at least partially in parallel relationship with one another [see Fig. 9A-9B, para. 114-117 as well as para. 125-129].
However, Yabe is silent with respect to adjacent ones of the plurality of active bit lines are spaced apart from one another by at least 30 nm.
Wolstenholme teaches adjacent ones of the plurality of active bit lines are spaced apart from one another by at least 30 nm [see Fig. 2, a distance full bit line pitch (FBLP) between the adjacent bitlines may comprise about 41 nm, para. 38].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Wolstenholme to the teachings of Yabe such that implement the bit line sensing scheme of Yabe on a 3D NAND array having the bit line geometry that adjacent ones of the plurality of active bit lines are spaced apart from one another by at least 30 nm as taught by Wolstenholme to achieve predictable result and reduce a copy time (e.g., time to copy a block of memory array) [see Wolstenholme’s para. 40].
Regarding claim 13, Yabe in combination with Wolstenholme teach the limitations with respect to claim 11.
Furthermore, Yabe discloses the memory block is a first memory block in a plane that includes a plurality of memory blocks that are in electrical communication with the set of bit lines, and wherein the plurality of memory blocks further includes a second memory block [see Fig. 4A, para 56-57].
Regarding independent claim 29, Yabe discloses a method of performing a sensing operation in a memory device [para. 125], comprising the steps of:
preparing a memory block that includes an array of memory cells arranged in a plurality of word lines [see Fig. 4C, one hundred and twenty-eight data word line layers WLL0-WLL127 for connecting to memory cells, para. 66] and in a plurality of memory holes [the non-volatile memory cells are formed along memory holes which extend through alternating conductive and dielectric layers in the stack, para. 70], the plurality of memory holes being in electrical communication with respective bit lines of a set of bit lines [see Fig. 4B, para. 61]; and
performing a read operation on a selected word line of the plurality of word lines in the memory block using a plurality of active bit lines of the set of bit lines, the active bit lines extending at least partially in parallel relationship with one another [see Fig. 9A-9B, para. 114-117 as well as para. 125-129].
However, Yabe is silent with respect to adjacent ones of the plurality of active bit lines being spaced apart from one another by at least 30 nm.
Wolstenholme teaches adjacent ones of the plurality of active bit lines being spaced apart from one another by at least 30 nm [see Fig. 2, a distance full bit line pitch (FBLP) between the adjacent bitlines may comprise about 41 nm, para. 38].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Wolstenholme to the teachings of Yabe such that implement the bit line sensing scheme of Yabe on a 3D NAND array having the bit line geometry that adjacent ones of the plurality of active bit lines are spaced apart from one another by at least 30 nm as taught by Wolstenholme to achieve predictable result and reduce a copy time (e.g., time to copy a block of memory array) [see Wolstenholme’s para. 40].
Allowable Subject Matter
Claims 12, 14-16, 24, 26-28 and 30-34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 12, the applied prior art, Yabe discloses a 3D NAND with memory holes and bit lines, where each of memory holes is tied to a corresponding bit line. Yabe does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Yabe is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Vollrath (US 6304479), which shows, in Figure 9, one bitline 1121 is connected on the right side of sense amplifier 116 and another bitline 1121 is connected on the left side of sense amplifier 116. Bitlines 1122 are disconnected from sense amplifiers 116 when bitlines 1121 are connected. Bitlines 1121 and 1122 are connected and disconnected from sense amplifiers 116, preferably by switches 120. However, the memory arrays of Vollrath are dynamic random access memories (DRAMS), not the non-volatile NAND memory. Vollrath also discloses bitlines 1122 are shown disconnected from sense amplifiers 116, then at a later time bitlines 1122 will be connected to sense amplifiers 216 and bitlines 1121 will be disconnected. So, these bitlines are still normal data bitlines, connected to memory cells 114. Vollrath does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Fifiled et al. (US 5010524), which show, in Figure 2, a pair BL2 and BL2' connected to sense amplifier 10 and inactive bit lines BL1, BL1', BL3, BL3' are isolated from their respective sense nodes by placing isolation devices 1, 2, 5 and 6 in a high impedance state. The inactive bit lines are effectively clamped to a fixed source of potential, preferably the same as used for precharging the bit lines prior to sensing. However, all these inactive bit lines are connected to DRAM memory cells. These inactive bit lines store and deliver data in other operations. There is no disclosure that these inactive bit lines are dummy, or that the associated memory cells cannot store data. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited of the set of bit lines further includes a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations.
With respect to claim 14, there is no teaching or suggestion in the prior art or record to provide the recited of further including circuitry that is in communication with the plurality of memory blocks, the circuitry being configured to perform a first read operation on the first memory block while the active bit lines of the set of bit lines are held at a first voltage that is greater than zero Volts, and without ramping the active bit lines of the set of bit lines down from the first voltage, perform a second read operation on a second memory block of the plurality of memory blocks while the active bit lines of the set of bit lines are held at the first voltage.
With respect to claim 16, there is no teaching or suggestion in the prior art or record to provide the recited of at least half of the memory holes of the plurality of memory holes are inactive memory holes that do not contain data.
With respect to claim 24, there is no teaching or suggestion in the prior art or record to provide the recited of the read operation includes discharging a plurality of sense nodes through the plurality of active bit lines and through a plurality of active memory holes of the plurality of memory holes while the plurality of inactive bit lines of the set of bit lines and a plurality of inactive memory holes of the plurality of memory holes remain inactive.
With respect to claim 26, there is no teaching or suggestion in the prior art or record to provide the recited of the memory block is a first memory block of a plurality of memory blocks, wherein the step of performing the read operation includes performing a first read operation on the first memory block of the plurality of memory blocks while a plurality of bit lines are held at a first voltage that is greater than zero Volts and further including the step of, without ramping the plurality of bit lines down from the first voltage, performing a second read operation on a second memory block of the plurality of memory blocks.
With respect to claim 28, there is no teaching or suggestion in the prior art or record to provide the recited of the plurality of memory holes includes active memory holes with memory cells that contain data and inactive memory holes with memory cells that do not contain data, and wherein at least half of the memory holes of the plurality of memory holes are inactive memory holes.
With respect to claim 30, the applied prior art, Yabe discloses a 3D NAND with memory holes and bit lines, where each of memory holes is tied to a corresponding bit line. Yabe does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Yabe is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Vollrath (US 6304479), which shows, in Figure 9, one bitline 1121 is connected on the right side of sense amplifier 116 and another bitline 1121 is connected on the left side of sense amplifier 116. Bitlines 1122 are disconnected from sense amplifiers 116 when bitlines 1121 are connected. Bitlines 1121 and 1122 are connected and disconnected from sense amplifiers 116, preferably by switches 120. However, the memory arrays of Vollrath are dynamic random access memories (DRAMS), not the non-volatile NAND memory. Vollrath also discloses bitlines 1122 are shown disconnected from sense amplifiers 116, then at a later time bitlines 1122 will be connected to sense amplifiers 216 and bitlines 1121 will be disconnected. So, these bitlines are still normal data bitlines, connected to memory cells 114. Vollrath does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Fifiled et al. (US 5010524), which show, in Figure 2, a pair BL2 and BL2' connected to sense amplifier 10 and inactive bit lines BL1, BL1', BL3, BL3' are isolated from their respective sense nodes by placing isolation devices 1, 2, 5 and 6 in a high impedance state. The inactive bit lines are effectively clamped to a fixed source of potential, preferably the same as used for precharging the bit lines prior to sensing. However, all these inactive bit lines are connected to DRAM memory cells. These inactive bit lines store and deliver data in other operations. There is no disclosure that these inactive bit lines are dummy, or that the associated memory cells cannot store data. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited of the set of bit lines further includes a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations.
With respect to claim 32, there is no teaching or suggestion in the prior art or record to provide the recited of the memory block is a first memory block of a plurality of memory blocks in a plane and wherein the read operation is a first read operation, and further including the steps of during the first read operation on the first memory block of the plurality of memory blocks, the plurality of active bit lines are held at a first voltage that is greater than zero Volts and without ramping the plurality of active bit lines down from the first voltage, performing a second read operation on a second memory block of the plurality of memory blocks while the plurality of active bit lines are held at the first voltage.
With respect to claim 34, there is no teaching or suggestion in the prior art or record to provide the recited of the plurality of memory holes includes active memory holes with memory cells that contain data and inactive memory holes with memory cells that do not contain data, and wherein at least half of the memory holes of the plurality of memory holes are inactive memory holes.
Claims 1-10 and 17-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 1, the applied prior art, Yabe discloses a 3D NAND with memory holes and bit lines, where each of memory holes is tied to a corresponding bit line. Yabe does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Yabe is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Vollrath (US 6304479), which shows, in Figure 9, one bitline 1121 is connected on the right side of sense amplifier 116 and another bitline 1121 is connected on the left side of sense amplifier 116. Bitlines 1122 are disconnected from sense amplifiers 116 when bitlines 1121 are connected. Bitlines 1121 and 1122 are connected and disconnected from sense amplifiers 116, preferably by switches 120. However, the memory arrays of Vollrath are dynamic random access memories (DRAMS), not the non-volatile NAND memory. Vollrath also discloses bitlines 1122 are shown disconnected from sense amplifiers 116, then at a later time bitlines 1122 will be connected to sense amplifiers 216 and bitlines 1121 will be disconnected. So, these bitlines are still normal data bitlines, connected to memory cells 114. Vollrath does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Fifiled et al. (US 5010524), which show, in Figure 2, a pair BL2 and BL2' connected to sense amplifier 10 and inactive bit lines BL1, BL1', BL3, BL3' are isolated from their respective sense nodes by placing isolation devices 1, 2, 5 and 6 in a high impedance state. The inactive bit lines are effectively clamped to a fixed source of potential, preferably the same as used for precharging the bit lines prior to sensing. However, all these inactive bit lines are connected to DRAM memory cells. These inactive bit lines store and deliver data in other operations. There is no disclosure that these inactive bit lines are dummy, or that the associated memory cells cannot store data. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited of the plurality of bit lines including a plurality of active bit lines that are in electrical communication with active sense amplifiers and memory cells during read operations, and the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations, in combination with other limitations.
With respect to independent claim 17, the applied prior art, Yabe discloses a 3D NAND with memory holes and bit lines, where each of memory holes is tied to a corresponding bit line. Yabe does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Yabe is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Vollrath (US 6304479), which shows, in Figure 9, one bitline 1121 is connected on the right side of sense amplifier 116 and another bitline 1121 is connected on the left side of sense amplifier 116. Bitlines 1122 are disconnected from sense amplifiers 116 when bitlines 1121 are connected. Bitlines 1121 and 1122 are connected and disconnected from sense amplifiers 116, preferably by switches 120. However, the memory arrays of Vollrath are dynamic random access memories (DRAMS), not the non-volatile NAND memory. Vollrath also discloses bitlines 1122 are shown disconnected from sense amplifiers 116, then at a later time bitlines 1122 will be connected to sense amplifiers 216 and bitlines 1121 will be disconnected. So, these bitlines are still normal data bitlines, connected to memory cells 114. Vollrath does not teach or suggest the plurality of bit lines including a plurality of inactive bit lines that are dummy and not in electrical communication with active memory holes during the read operations. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Another prior art is Fifiled et al. (US 5010524), which show, in Figure 2, a pair BL2 and BL2' connected to sense amplifier 10 and inactive bit lines BL1, BL1', BL3, BL3' are isolated from their respective sense nodes by placing isolation devices 1, 2, 5 and 6 in a high impedance state. The inactive bit lines are effectively clamped to a fixed source of potential, preferably the same as used for precharging the bit lines prior to sensing. However, all these inactive bit lines are connected to DRAM memory cells. These inactive bit lines store and deliver data in other operations. There is no disclosure that these inactive bit lines are dummy, or that the associated memory cells cannot store data. Or as claimed, Vollrath is silent to “the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations”.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited of the plurality of bit lines including a plurality of active bit lines that are in electrical communication with active sense amplifiers and memory cells during read operations, and the plurality of bit lines including a plurality of inactive bit lines that are not in electrical communication with active sense amplifiers or memory cells during the read operations, in combination with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825