DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 12/26/2025. Claims 1-17 are pending in the Application, of which Claims 1, 7 and 15 are independent.
Continuity/ Priority Information
The present Application 18679452 filed 05/31/2024 claims foreign priority to REPUBLIC OF KOREA10-2023-0197276, filed 12/29/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments, see Amendment/ Remarks filed 12/26/2025 with respect to the rejection of claims 1-17 under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (U.S. Patent No. 9,583,215), have been considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Ichiriu et al. (U.S. Patent No. 7,043,673) Pub. Date: 2006-05-09, as set forth in the present office action
Claim rejections under 35 USC 112b is withdrawn due to Applicant’s amendment to the Claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, “an error counter configured to generate symbol information indicating a number of errors occurring in the first or second part of the plurality of test data” is indefinite. It is unclear whether the counter generates a number, or a symbol. Normally, the intended use of the counter is to count, i.e. counting the number of error bits, as in the instant Application. The specification is insufficient in describing the generation of symbol information by the counter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ichiriu et al. (U.S. Patent No. 7,043,673) Pub. Date: 2006-05-09.
Regarding independent Claims 1, 7 and 15, Ichiriu discloses Content Addressable Memory With Priority-biased Error Detection Sequencing, comprising:
a memory circuit configured to generate a plurality of in a test mode; and configured to generate first comparison signals based on a first part of the plurality of test data and a first part of a plurality of reference, and generate second comparison signals based on a second part of the plurality of test data and a second part of the plurality of reference during a first and second read operation period, respectively;
FIG. 1 illustrates a CAM device 100 that includes a CAM array 101 “memory circuit” having a plurality of CAM cells arranged in rows for storing CAM words.
FIG. 6 illustrates the error detector 107 of FIG. 1. As shown, a CAM word formed by of N groups of M data bits is output from the sense amplifier bank 162. The first group of data bits is designated D[M-1, 0], corresponding to “a first part of the plurality of test data and a first part of a plurality of reference” the second group of data bits is designated D[(2.times.M)-1, M] corresponding to “a second part of the plurality of test data and a second part of the plurality of reference” and so forth to the final group of data bits designated D[(N.times.M)-1, (N-1).times.M]. The CAM word also includes N parity bits “test data\”, one for each group of M bits.
an error counter configured to generate first symbol information indicating a first number of errors occurring in the first part of the plurality of test data, and generate second symbol information indicating a second number of errors occurring in the second part of the plurality of test data;
Returning to FIG. 6, the compare circuit 208 compares the output of the parity generator 206 with the corresponding stored parity bit. Compare circuit 208 is preferably a combinatorial logic circuit such as an XOR circuit that outputs a logic `1` only if the stored parity bit and the parity bit generated by the parity generator 206 do not match, corresponding to “error”, but may alternatively be any type of circuit for detecting mismatch between the stored and generated parity bits, corresponding to “symbol information”. The outputs of all the compare circuits 208 are logically ORed in gate 221 so that, if any one of the compare circuits 208 signals a mismatch (i.e., a logical `1`), the parity check circuit 201 will output a logical `1`.
an error determiner configured to generate a pass/fail signal indicating whether the memory circuit is normal, based on the first and second symbol information.
FIG. 6, The parity error signal 231 “pass/fail signal” is supplied to the set input of an S-R flip-flop and to the load input of an error address register 203. The check address 155 from the check address generator (element 124 of FIG. 2), which constitutes a parity address in this example, is also input to the error address register 203 so that, if the parity error signal 231 is asserted, the parity address is loaded into the error address register 203. Still referring to FIG. 6, the S-R flip-flop 224, when set, drives the error flag signal 132 “pass/fail signal”. As described above, the error flag signal 132 is preferably output directly to a host device to signal the error condition, but may alternatively (or additionally) be output as part of a status word during a host-requested status read operation.
Regarding Claims 2, 8, 9, 10, Ichiriu discloses configured to compare P bits among K bits included in a first burst length with P bits among K bits included in the burst length of corresponding reference data;
FIG. 6, The data and parity bits are input to a parity check circuit 201 that includes a separate parity generator 206 and compare circuit 208 “P comparators” for each group of data bits and its corresponding parity bit. Each parity generator 206 generates a binary output according to the state of an even/odd select signal 232 and the number of set (or reset) data bits within the corresponding group of data bits.
Regarding Claims 3, 11, 15, Ichiriu discloses wherein the error counter includes a plurality of stages, FIG. 23 illustrates a counter 700 that may be used to generate a linear sequence of error check addresses within a CAM device. The counter 700 maintains an internal count value which is output as the check address 155 described above and which is incremented (or decremented) by a predetermined value in response to a rising (or falling) edge of an enable signal 126 at a strobe input of the counter 700. When a final count is reached, the count value, and therefore the check address, is rolled over to an initial value to repeat the sequence.
Regarding Claims 4, 5, 12, 13, Ichiriu discloses the error determiner includes: a latch circuit configured to latch the first symbol information;
Still referring to FIG. 6, the S-R flip-flop 224 “latch circuit”, when set, drives the error flag signal 132. The reset signal 153 is received from the instruction decoder as shown in FIG. 1 and is used to clear the error flag signal by resetting the S-R flip-flop 224.
Regarding Claims 6, 14, 17, Ichiriu discloses the memory circuit reads a plurality of normal data in a normal mode, and wherein, the error check circuit checks the number of errors occurring in the normal data.
FIG. 1,The read/write circuit 161 is used to sense the output of the selected row during a read operation and to transmit a value to the selected row during a write operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 16, 2026
Final Rejection 20260117
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV