DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 04/21/2026. Claims 1-17 are pending in the Application, of which Claims 1, 7 and 15 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/21/2026 has been entered.
Continuity/ Priority Information
The present Application 18679452 filed 05/31/2024 claims foreign priority to REPUBLIC OF KOREA10-2023-0197276, filed 12/29/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments, see Amendment/ Remarks filed 04/21/2026 with respect to the rejection of claims 1-17 under 35 U.S.C. 102(a)(1) as being anticipated by Ichiriu et al. (U.S. Patent No. 7,043,673), have been considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of MAHESHWAR et al. (Pub. No. US 20180067164) Pub. Date: 2018-03-08, as set forth in the present office action.
Claims rejections under 35 USC 112b is withdrawn due to Applicant’s amendment /remarks.
The Examiner agrees with Applicant’s argument, that the CAM device of Ichiriu is not designed to operate in test mode or to "generate a pass/fail signal indicating whether the memory circuit is normal, based on the first and second symbol information" but rather to detect soft errors every time the system needs to search or write to the associated memory.
However, under a new ground(s) of rejection, MAHESHWAR discloses the above limitations, i.e. a device under test to operate in a test mode and to "generate a pass/fail signal, as set forth in the present office action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MAHESHWAR et al. (Pub. No. US 20180067164) Pub. Date: 2018-03-08.
Regarding independent Claims 1, 7 and 15, MAHESHWAR discloses systems and methods that facilitate analysis of digital circuitry using multiple input signature register (MISR) architectures comprising.
a memory circuit configured to generate a plurality of test data in a test mode; [0019] FIG. 1, a multiple input signature register (MISR) 110 is activated to compress M different scan chains, shown as scan chains 1 though M, from N different scan inputs 114 to which test patterns “test data” are applied, where M and N are positive integers. Each of the scan chains 1 though M holds one or more test data bits to test the integrated circuit. The data in the respective scan chains reflects output responses from the circuit under test as stimulated by the expanded test patterns generated by the decompressor 120.
a plurality of comparator groups configured to generate first comparison signals based on a first part of the plurality of test data and a first part of a plurality of reference data during a first read operation period, and generate second comparison signals based on a second part of the plurality of test data and a second part of the plurality of reference data during a second read operation period; an error counter configured to generate first symbol information indicating a first number of errors occurring in the first part of the plurality of test data, and generate second symbol information indicating a second number of errors occurring in the second part of the plurality of test data; [0020] A shift register 130 “error counter” can be loaded from an interface 140 and holds one of N comparison signatures that is used to validate one of the N test signatures in the MISR 110. The interface 140 can be implemented as a joint test action group (JTAG) interface or an IEEE 1500 interface. Other interfaces are possible including custom interfaces (serial or parallel). In an alternative example, the shift register 130 may not be provided. Instead, the contents of the MISR 110 can be shifted out directly via the interface 140 for comparison with the comparison signatures described herein.
an error determiner configured to generate a pass/fail signal indicating whether the memory circuit is normal. [0021] A comparator 150 compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison. The comparator 150 can determine the failure condition if the comparison (e.g., a bitwise comparison) indicates one or more bits of the test signature do not match one or more bits of the comparison signature.
[0026] After the complete shift-out of each pattern, the cumulated MISR signature is compared with the expected signature where the comparator 150 compares the values in MISR 110 and the shift register 130, using a bit-wise comparison. A single bit Fail/Pass status can be strobed at the output of the comparator 150 depending on the results of the comparison.
Regarding Claims 2, 8, 9, 10, MAHESHWAR discloses configured to compare P bits among K bits included in a first burst length with P bits among K bits included in the burst length of corresponding reference data;
Regarding Claims 3, 11, 15, MAHESHWAR discloses wherein the error counter includes a plurality of stages, [0022] A processor 160 operates the interface 140 to control loading/unloading of the shift register 130 corresponding to “error counter” and to control data exchanges between the MISR 110 and the shift register 130. In one example, the processor 160 retrieves the comparison signatures from an expected signature memory 170 (e.g., file or memory location) and loads the shift register 130 via the interface. In another example, the processor 160 can be provided as an on-chip controller to access the MISR 110 and/or shift register 130 via the interface 140.
Regarding Claims 4, 5, 12, 13, MAHESHWAR discloses the error determiner includes: a latch circuit configured to latch the first symbol information; [0024] The logging system 174 can be executed as part of an automatic test-pattern generator (ATPG) and/or in accordance with operations of the processor 160 which can also be part of the ATPG (e.g., the comparator 150 can provide the results of the comparison to the processor 160 or directly to memory accessible by the processor). If any failed patterns are detected, the processor 160 during a subsequent per cycle/debug phase of the integrated circuit provides the failed test pattern from the log file 180 to the ATPG to enable the scanned chains to be loaded in response to the failed test pattern.
Regarding Claims 6, 14, 17, MAHESHWAR discloses the memory circuit reads a plurality of normal data in a normal mode, and wherein, the error check circuit checks the number of errors occurring in the normal data. [0035] The circuit 300 also includes an N-bit bitwise comparator 350, such as corresponding to comparators 150 and 270. The comparator 350 can compare the values in shift register containing the expected MISR signature and the MISR containing the calculated MISR signature, and provides a single bit pass/fail status condition for each pattern which can be logged out on a test pin, thus enabling per pattern signature comparison.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20100218059 Gangasani; Swathi et al. [0006] After 32 captures (known as one interval) in multiple-input signature register (MISR) 105, the state of the signature analyzer output via MISR_Scan_out is compared to the known signature of the fault free design. Any mismatch indicates that at least one erroneous value was unloaded from the scan chains. Multiple-input signature register (MISR) 104 is a modified LFSR. Compactor 104 is made of combinational logic.
US 20070143651 Kiryu; Naoki [0038] As a shown in the FIG. 2, operation of the test system begins with initialization phase 201. As noted above, the various components of the system are prepared for normal operation during this phase. It may be necessary to ensure that several registers (e.g., test counter register, scan-shift counter register, bit monitor register) have the appropriate values stored therein.
US 6058056 Beffa; Ray et al. See, Abstract. A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: May 15, 2026
Non-Final Rejection 20260515
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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