DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 05/31/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
Figures 1, 2, 3, 4, 7A, 7B, 7C, 7D, 8, 9, 10A, 10B, 11 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Instant application Figures 1, 4, 5, 5C, 6A, 7A, 7B, 7C, 7D, 8A, 9, 10A, 10B, 11A are identical to Sandisk’s previously published patent No. 11,222,678 B1.
These references have been added to form PTO-892 to reflect consideration. Applicant is reminded of the helpful scenarios in MPEP 2004, such as scenario 7 (characterizing information), and MPEP 2011(on how to correct the record).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-9’s “one or more control circuit” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Regarding Independent Claims 19-20 are claimed on the elements “means for reading…” is a means (or step) plus function limitation that invokes 35 U.S.C. 112 (f). However, the written description fails to disclose the corresponding structure, material, or acts for the claimed function. Blocks R/W circuit 516 is not shown in enough detail to warrant protection under 35 USC 112(f). A generic box with a label does not sufficiently describe the underlying structure that performs the recited function.
Applicant is required to:
(a) Amend the claim so that the claim limitation will no longer be a means (or step) plus function limitation under 35 U.S.C. 112 (f); or
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the claimed function without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant is required to clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-12, 19-20 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Robertson et al (US 11,501,831 B2 hereinafter “Robertson”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Robertson, for example in Figs. 1-18, discloses an apparatus (e.g., 500; in Fig. 5 related in Figs. 1-4, 6-18), comprising: one or more control circuits (included 510, 520, 560; in Fig. 5 related in Figs. 1-4, 6-18) configured to connect to a multi-story nonvolatile memory structure (see for example in Figs. 9-11 related in Figs. 1-8, 12-18) that includes nonvolatile memory cells (e.g., 701; in Figs. 7A, 7D related in Figs. 1-6, 8-18) each having a programmable resistive element (see for example in Figs. 7-11 related in Figs. 1-6, 12-18), the one or more control circuits configured to: receive addresses of selected nonvolatile memory cells (see for example in Fig. 5 related in Figs. 1-4, 6-18) and for each selected nonvolatile memory cell determine a story in which the selected nonvolatile memory cell is located from a plurality of stories including a first story between a first word line layer (see for example in Figs. 7-11 related in Figs. 1-6, 12-18) and a bit line layer and a second story between the bit line layer and a second word line layer (see for example in Figs. 7-11 related in Figs. 1-6, 12-18), connect a sense amplifier to a first selected nonvolatile memory cell in the first story through a bit line of the bit line layer (e.g., 560; in Fig. 5 related in Figs. 1-4, 6-18) and connect the sense amplifier to a second selected nonvolatile memory cell in the second story through a second word line of the second word line layer (see for example in Fig. 5 related in Figs. 1-4, 6-18).
For apparatus claims 1-7, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Robertson et al. disclose a substantially identical memory apparatus; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 2, Robertson, for example in Figs. 1-18, discloses wherein the first selected nonvolatile memory cell includes a selector (e.g., 1109; in Figs. 11A, 11B related in Figs. 1-10, 12-18) in contact with a first word line of the first word line layer (e.g., 1100; in Figs. 11A, 11B related in Figs. 1-10, 12-18) and an MRAM cell formed between the selector and the bit line (e.g., 1102; in Figs. 11A, 11B related in Figs. 1-10, 12-18, as discussed above).
Regarding claim 3, Robertson, for example in Figs. 1-18, discloses wherein the second selected nonvolatile memory cell includes a selector in contact with the bit line (e.g., 1119; in Figs. 11A, 11B related in Figs. 1-10, 12-18) and an MRAM cell formed between the selector and the second word line (see for example in Figs. 11A, 11B related in Figs. 1-10, 12-18, as discussed above).
Regarding claim 4, Robertson, for example in Figs. 1-18, discloses wherein the one or more control circuits are further configured to connect a first voltage to the first selected nonvolatile memory cell through a first word line of the first word line layer (see for example in Figs. 7-11 related in Figs. 1-63, 12-18, as discussed above) and connect a second voltage that is less than the first voltage to the bit line for reading the first selected nonvolatile memory cell (see for example in Figs. 7-11 related in Figs. 1-63, 12-18, as discussed above).
Regarding claim 5, Robertson, for example in Figs. 1-18, discloses wherein the one or more control circuits are further configured to connect the first voltage to the second selected nonvolatile memory cell through the bit line (see for example in Figs. 7-11 related in Figs. 1-63, 12-18, as discussed above) and connect the second voltage to the second selected nonvolatile memory cell through the second word line (see for example in Figs. 7-11 related in Figs. 1-63, 12-18, as discussed above).
Regarding Independent Claim 10, Robertson, for example in Figs. 1-18, discloses a method, comprising: receiving a first address of a first selected nonvolatile memory cell (e.g., 701/1152 and 1159/1162 and 1169; in Figs. 7A, 7D, 11A, 11B related in Figs. 1-6, 8-10, 12-18) at an intersection of a first word line (e.g., 1100/1120; in Figs. 11A, 11B related in Figs. 1-10, 12-18) and a first bit line in a nonvolatile memory cell structure (e.g., 1160; in Figs. 11A, 11B related in Figs. 1-10, 12-18); determining that the first selected nonvolatile memory cell is in a first story (e.g., 1152/1162; in Figs. 11A, 11B related in Figs. 1-10, 12-18); in response to determining that the first selected nonvolatile memory cell is in the first story (see for example in Figs. 7-11 related in Figs. 1-6, 12-18), connecting a sense amplifier to the first bit line to read the first selected nonvolatile memory cell (within 560; in Fig. 5 related in Figs. 1-4, 6-18); receiving a second address of a second selected nonvolatile memory cell (.g., 701/1152 and 1159/1162 and 1169; in Figs. 7A, 7D, 11A, 11B related in Figs. 1-6, 8-10, 12-18) at an intersection of the first bit line (see for example in Figs. 7-11 related in Figs. 1-6, 12-18) and a second word line in the nonvolatile memory cell structure (e.g., 1120/1100; in Figs. 11A, 11B related in Figs. 1-10, 12-18); determining that the second selected nonvolatile memory cell is in a second story (e.g., 1162/1152; in Figs. 11A, 11B related in Figs. 1-10, 12-18); and in response to determining that the second selected nonvolatile memory cell is in the second story, connecting the sense amplifier to the second word line to read the second selected nonvolatile memory cell (see for example in Figs. 7-11 related in Figs. 1-6, 12-18).
For method claims 10-14, MPEP 2112.02(I) instructs examiners, “When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process.” Applicant’s only disclosed device is shown in instant application Figures 1, 4, 5, 7A, 7B, 7C, 7D, 8, 9, 10A, 10B, 11, which are identical to Robertson et al. Figures 1, 5, 6A, 7A, 7B, 7C, 7D, 8, 9, 10A, 10B, 11. Per MPEP 2112.02(I), Robertson et al.’s identical device is assumed to inherently perform the claimed process. see also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 11, Robertson, for example in Figs. 1-18, discloses further comprising: connecting a first voltage to the first word line and a second voltage that is less than the first voltage to the first bit line to read the first selected nonvolatile memory cell (e.g., 1102; in Figs. 11A, 11B related in Figs. 1-10, 12-18, as discussed above).
Regarding claim 12, Robertson, for example in Figs. 1-18, discloses further comprising: connecting the first voltage to the first bit line and the second voltage to the second word line to read the second selected nonvolatile memory cell (e.g., 1102; in Figs. 11A, 11B related in Figs. 1-10, 12-18, as discussed above).
Regarding Independent Claim 19, Robertson, for example in Figs. 1-18, discloses a system (e.g., 100; in Fig. 1 related in Figs. 2-198), comprising: a nonvolatile memory cell structure (see for example in Figs. 7-11 related in Figs. 1-6, 12-18) that includes nonvolatile memory cells in a cross-point arrangement (see for example in Figs. 7-11 related in Figs. 1-6, 12-18), each memory cell having a programmable resistive element (e.g., 1152/1162; in Figs. 11A, 11B related in Figs. 1-10, 12-18); and means for reading nonvolatile memory cells that are located in a plurality of stories including a first story (e.g., Layer ½ Cell; in Figs. 11A, 11B related in Figs. 11-10, 12-18) between a first word line layer (e.g., 1150/1170; in Figs. 11A, 11B related in Figs. 1-10, 12-18) and a bit line layer (e.g., 1160; in Figs. 11A, 11B related in Figs. 1-10, 12-18) and a second story between the bit line layer and a second word line layer (e.g., 1170/1150; in Figs. 11A, 11B related in Figs. 1-10, 12-18) including connecting a sense amplifier (e.g., 560; in Figs. 5 related in Figs. 1-4, 6-18) to a first selected nonvolatile memory cell in the first story through a bit line of the bit line layer and connecting the sense amplifier to a second selected nonvolatile memory cell in the second story through a second word line of the second word line layer (see for example in Figs. 5 related in Figs. 1-4, 6-18).
For apparatus claims 19-20, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Robertson et al. disclose a substantially identical memory apparatus; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 20, Robertson, for example in Figs. 1-18, discloses wherein each nonvolatile memory cell in the first story includes a selector located between an MRAM cell and the first word line layer (see for example in Figs. 7-11 related in Figs. 1-6, 12-18, as discussed above), the MRAM cell located between the selector and the bit line layer and each nonvolatile memory cell in the second story includes a selector located between an MRAM cell and the bit line layer, the MRAM cell located between the selector and the second word line layer (see for example in Figs. 7-11 related in Figs. 1-6, 12-18, as discussed above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Robertson et al (US 11,501,831 B2 hereinafter “Robertson”) in view of Wells et al (US 8,144,506 B2 hereinafter “Wells”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 6, Robertson, for example in Figs. 1-18, discloses the claimed invention as discussed above. However, Robertson is silent with regard to wherein the first voltage is a positive voltage and the second voltage is a negative voltage.
In the same field of endeavor, Wells, for example in Figs. 1-5, discloses wherein the first voltage is a positive voltage and the second voltage is a negative voltage (e.g., Vo/2 or -Vo/2; in Fig. 5 related in Figs. 1-4).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Robertson such as power off recovery in cross-point memory with threshold switching selectors (see for example in Figs. 1-18 of Robertson) by incorporating the teaching of Wells such as cross-point memory devices, electronic system including cross-point memory devices and method of accessing a plurality of memory cells in a cross-point memory array (see for example in Figs. 1-5 of Wells), for the purpose of controlling the control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines (Wells, see Abstract).
Regarding claim 7, the above Robertson/Wells, the combination discloses wherein the first voltage is between 2.5 volts and 3.0 volts and the second voltage is between -2.5 volts and -3.0 volts (see for example in Figs. 1-18 of Robertson and also see in Figs. 1-5 of Wells, as discussed above).
Regarding claim 13, the above Robertson/Wells, the combination discloses wherein the first voltage is a positive voltage and the second voltage is a negative voltage (see for example in Figs. 1-18 of Robertson and also see in Figs. 1-5 of Wells, as discussed above).
Regarding claim 14, the above Robertson/Wells, the combination discloses wherein the first voltage is between 2.5 volts and 3.0 volts and the second voltage is between -2.5 volts and -3.0 volts (see for example in Figs. 1-18 of Robertson and also see in Figs. 1-5 of Wells, as discussed above).
Allowable Subject Matter
Claims 8-9, 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior arts of record fail to teach or suggest a semiconductor memory device as recited in claim 8, and particularly, wherein the one or more control circuits include a first plurality of switches connected between the first voltage and the bit line, a second plurality of switches connected between the bit line and the sense amplifier, a third plurality of switches connected between the first voltage and the first word line and a fourth plurality of switches connected between the first word line and the sense amplifier.
Regarding claim 15, the prior arts of record fail to teach or suggest a method as recited in claim 8, and particularly, further comprising: passing a first current through the first word line, the first selected nonvolatile memory cell, the first bit line and a current mirror to read the first selected nonvolatile memory cell; and sensing the first selected nonvolatile memory cell by the sense amplifier by comparing a sense voltage between the first bit line and the current mirror with a reference voltage while passing the first current.
Regarding claim 17, the prior arts of record fail to teach or suggest a method as recited in claim 8, and particularly, wherein connecting the sense amplifier to the first bit line to read the first selected nonvolatile memory cell includes turning on a first plurality of NMOS transistors connected between the first bit line and the sense amplifier while a first plurality of PMOS transistors connected between the first bit line and a supply voltage are turned off and a second plurality of PMOS transistors connecting the first word line with the supply voltage are turned on.
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THA-O H BUI whose telephone number is (571)270-7357. The examiner can normally be reached M-F 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER SOFOCLEOUS can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THA-O H BUI/Primary Examiner, Art Unit 2825 12/03/2025