DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 3, claims 1-7, 9 and 10, in the reply filed on July 28, 2026 is acknowledged. The traversal is on the ground(s) that the search can be made without serious burden. The Examiner respectfully disagrees. This is not found persuasive because all of the species mentioned in the election/restriction requirement filed July 22, 2026 all have distinct structural configurations which would require the Examiner to search various CPC and USPC scheme for each individual species due their structural differences. This would require the Examiner to develop five different search strategies for each species/invention. Lastly, the MPEP states that there can be only one patent per invention, hence one invention per application.
The requirement is still deemed proper and is therefore made FINAL. Claims 8 and 11-20 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Kim) (US 2021/0159213 A1).
In regards to claim 1, Kim (Figs. 8, 9A, 9B and associated text) discloses a semiconductor package (item 10C) comprising: a package substrate (item 100) including an insulating layer (item 101, paragraph 29), an interconnection layer (not shown but mentioned, paragraphs 27, 29) in the insulating layer (item 101, paragraph 29), and interconnection pads (item 103B) on the insulating layer (item 101) and electrically connected to the interconnection layer (not shown but mentioned, paragraphs 27, 29); first and second lower semiconductor chips (items 210 and 220) over the package substrate (item 100), the first and second lower semiconductor chips (items 210 and 220, 210 and 230 or 230 and 220) spaced apart from each other in a first direction; first connection wires (item 215, 225 or 235) extending from a first side of the first lower semiconductor chip (items 210, 220 or 230) towards a second side of the second lower semiconductor chip (items 210, 220 or 230), the first connection wires (item 215, 225 or 235) spaced apart from each other in a second direction, the second direction intersecting the first direction; an adhesive layer (item 317) over the first and second lower semiconductor chips (items 210 and 220, 210 and 230 or 230 and 220), the adhesive layer (item 317) covering at least a portion of each of the first connection wires (item 215, 225 or 235); an upper semiconductor chip (item 300) over the adhesive layer (item 317); second connection wires (item 215, 225, 235 or 315) electrically connecting the first and second lower semiconductor chips (items 210 and 220, 210 and 230 or 230 and 220) and the upper semiconductor chip (item 300) to the interconnection layer (not shown but mentioned, paragraphs 27, 29) of the package substrate (item 100); and an encapsulant (item 500) on the package substrate (item 100), the encapsulant (item 500) filling a space between the first and second lower semiconductor chips (items 210 and 220, 210 and 230 or 230 and 220).
In regards to claim 2, Kim (Figs. 8, 9A, 9B and associated text) discloses wherein the first lower semiconductor chip (items 210, 220 or 230) further includes first dummy pads (items 217, 233 or 223) adjacent to the first side, the second lower semiconductor chip (items 210, 220 or 230) further includes second dummy pads (items 217, 233 or 223) adjacent to the second side, and each of the first connection wires (item 215, 225 or 235) connects a first dummy pad (items 217, 233 or 223), of the first dummy pads (items 217, 233 or 223), to a corresponding second dummy pad (items 217, 233 or 223) of the second dummy pads (items 217, 233 or 223). What is the second side? Second top side?
In regards to claim 3, Kim (Figs. 8, 9A, 9B and associated text) discloses wherein the first and second dummy pads (items 217 and 223 or 233 and 223) are located at a same level.
In regards to claim 4, Kim (Figs. 8, 9A, 9B and associated text) discloses wherein an upper surface of the first and second lower semiconductor chips (items 210 and 220, 210 and 230 or 230 and 220) are located at a same level.
In regards to claim 5, Kim (Figs. 8, 9A, 9B and associated text) discloses further comprising: a third lower semiconductor chip (item 230) between the first and second lower semiconductor chips (items 210 and 220); and third connection wires (item 235) connecting at least one of the first and second lower semiconductor chips (items 210 and 220) to the third lower semiconductor chip (item 230).
In regards to claim 6, Kim (Figs. 8, 9A, 9B and associated text) discloses wherein an upper surface of the third lower semiconductor chip (item 230) is located at a same level as upper surfaces of the first and second lower semiconductor chips (items 210 and 220).
In regards to claim 7, Kim (Figs. 8, 9A, 9B and associated text) discloses wherein the first connection wires (item 215 or 225) and the third connection wires (item 235) are spaced apart from each other in the second direction.
In regards to claim 9, Kim (Figs. 8, 9A, 9B and associated text) discloses further comprising: adhesive members (items 217, 227) attaching the first and second lower semiconductor chips (items 210 and 220) to the package substrate (item 100), wherein a height of the adhesive layer (item 317) is greater than heights of the adhesive members (items 217, 227).
In regards to claim 10, Kim (Figs. 8, 9A, 9B and associated text) discloses wherein at least a portion of each of the first connection wires (item 215, 225 or 235) crosses a region between the first side and the second side when viewed in cross section.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) (US 2021/0159213 A1) in view of Michikoshi (US2020/0176424 A1).
In regards to claim 6, Kim (Figs. 8, 9A, 9B and associated text) does not specifically wherein an upper surface of the third lower semiconductor chip (item 230) is located at a same level as upper surfaces of the first and second lower semiconductor chips (items 210 and 220).
Michikoshi (Fig. 4A and associated text) discloses wherein an upper surface of the third lower semiconductor chip (item 33) is located at a same level as upper surfaces of the first and second lower semiconductor chips (items 32 and 34).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Michikoshi for the purpose of less stress and stable signals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 August 5, 2026
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