Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 31, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Nakabayashi (US 20220399297 A1) in view of Takami et al. (JP 2014192363 A)
Regarding Claim 1 – Nakabayashi teaches a terminal structure, comprising: a first wiring layer (Fig 2; 31); an insulation layer covering the first wiring layer (Fig 2; 40; Nakabayashi [0030] states “The insulation layer 40 is formed… so as to partially cover the wiring layer 31”); an opening extending through the insulation layer in a thickness-wise direction and partially exposing an upper surface of the first wiring layer (Nakabayashi [0031] states “The insulation layer 40 includes openings 41 extending through the insulation layer 40 in the thickness-wise direction and partially exposing the upper surface of the wiring layer 31”); via wiring formed in the opening (Nakabayashi [0034] states “The connection terminal 50 includes… a via wiring 51 that is formed in the corresponding opening 41” and [0035] states “The opening 41 is… filled with the via wiring 51”); a second wiring layer electrically connected to the via wiring and formed on an upper surface of the insulation layer (Nakabayashi [0034] states “a wiring layer 52 that is electrically connected to the wiring layer 31 by the via wiring 51 and formed on the upper surface of the insulation layer 40”, additionally Nakabayashi [0064] states “the wiring layer 52 is one example of a second wiring layer.”); a protective metal layer formed on an upper surface of the second wiring layer (Nakabayashi [0041] states “The protective metal layer 60 is formed on the upper surface of the wiring layer 52 (metal post 55). The protective metal layer 60 covers… the entire upper surface of the wiring layer 52”); a solder layer formed on an upper surface of the protective metal layer (Nakabayashi [0047] states “The solder layer 70 is formed on the upper surface of the protective metal layer 60… covers the entire upper surface of the protective metal layer 60… covers the side surface of the protective metal layer 60”); and an intermetallic compound layer formed at an interface between the protective metal layer and the solder layer (Nakabayashi [0051] states “An intermetallic compound layer 80 is formed at an interface (bonding interface) of the protective metal layer 60 and the solder layer 70”), wherein the protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer (Nakabayashi [0044] states “The protective metal layer 60 includes a projection 61 projecting further outward from a position corresponding to the side surface of the wiring layer 52”); the intermetallic compound layer exposes the side surface of the second wiring layer (Nakabayashi [0051] states “the side surface of the wiring layer 52 is exposed from the intermetallic compound layer 80”); the solder layer exposes the side surface of the second wiring layer (Nakabayashi [0047] states “The side surface of the wiring layer 52 is exposed from the solder layer 70”).
Nakabayashi does not explicitly disclose the intermetallic compound layer covers only the upper surface of the protective metal layer and exposes a side surface of the protective metal layer, and the solder layer covers only an upper surface of the intermetallic compound layer and exposes a side surface of the intermetallic compound layer, and the side surface of the protective metal layer.
Takami teaches when adding both additional metal layers as well as a solder layer leaving the sides of the structure exposed as disclosed with the intermetallic compound layer covers only the upper surface of the protective metal layer and exposes a side surface of the protective metal layer, and the solder layer covers only an upper surface of the intermetallic compound layer and exposes a side surface of the intermetallic compound layer, and the side surface of the protective metal layer (Figs 2/3; B1/12/10; Takami [0012] states “The solder bump is deposited only on the upper surface of the pad, and the solder bump is welded only on the nickel plating layer” and Takami [0014] states “the solder bumps do not go around the side surfaces of the semiconductor element connection pads.” Fig 2 shows B1 located on the upper surface region while the side surfaces of the intermediate layers beneath B1 remain exposed, thereby teaching the claimed configuration that the solder layer covers only an upper surface and exposes side surfaces of underlying layers).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nakabayashi with the intermetallic compound layer covers only the upper surface of the protective metal layer and exposes a side surface of the protective metal layer, and the solder layer covers only an upper surface of the intermetallic compound layer and exposes a side surface of the intermetallic compound layer, and the side surface of the protective metal layer as taught by Takami and further consistent with Nakabayashi [0051] stating “An intermetallic compound layer 80 is formed at an interface (bonding interface) of the protective metal layer 60 and the solder layer 70” because Takami confines solder to the upper surface region and avoids solder wrapping around the side surfaces simplifying the manufacturing process, reducing the material usage, thereby saving cost, and improves insulation reliability (Takami [0009] explains that when solder “wrap around to the side surfaces” of pads, “the insulation gap… is narrowed” and “electrical insulation reliability… is lowered”).
Regarding Claim 5 – Nakabayashi in view of Takami teaches the terminal structure according to claim 1, wherein the opening is filled with the via wiring (Fig 2; Nakabayashi [0035] states “The opening 41 is… filled with the via wiring 51”), and the second wiring layer has the form of a post extending upward from the upper surface of the insulation layer (Fig 2; Nakabayashi [0039] states “The wiring layer 52… is formed on the upper surface of the insulation layer 40” and the described metal post 55 supports the post form).
Regarding Claim 6 – Nakabayashi in view of Takami teaches the terminal structure according to claim 1, wherein the via wiring is shaped in conformance with a wall surface of the opening (Fig 2; Nakabayashi [0035] states “The via wiring 51 may be shaped in conformance with the opening 41”), the upper surface of the second wiring layer includes a second recessed portion recessed toward the first wiring layer (Fig 11; Nakabayashi [0088] states “The wiring layer 52 may include a recess 52X that is recessed from the upper surface of the wiring layer 52 toward the wiring layer 31”), the upper surface of the protective metal layer includes a third recessed portion recessed toward the first wiring layer (Fig 11; Nakabayashi [0088] states “The protective metal layer 60 may include a recess 60X that is recessed from the upper surface of the protective metal layer 60 toward the wiring layer 31”), and the third recessed portion is filled with the solder layer (Fig 11; Nakabayashi [0089] states “the solder layer 70 fills the recess 60X”).
Regarding Claim 7 – Nakabayashi in view of Takami teaches the terminal structure according to claim 1, wherein the intermetallic compound layer is formed through reaction between a metal of the protective metal layer and a metal of the solder layer (Nakabayashi [0052] states “The intermetallic compound layer 80 is formed through… reaction of the metal (e.g., Ni) forming the protective metal layer 60 with the metal (e.g., Sn) forming the solder layer 70”).
Regarding Claim 8 – Nakabayashi in view of Takami teaches the terminal structure according to claim 1, wherein the second wiring layer includes Cu (Nakabayashi [0039] states “The material of the metal post 55 may be… copper or a copper alloy” and “The wiring layer 52… is formed by the metal post 55”), the protective metal layer includes Ni (Nakabayashi [0042] states “the protective metal layer 60 is an Ni layer”), the solder layer includes Sn (Nakabayashi [0049]), and the intermetallic compound layer Cu, Ni, and Sn (Nakabayashi [0052]).
Regarding Claim 9 – Nakabayashi in view of Takami teaches a wiring substrate, comprising: the terminal structure according to claim 1 (Figs 1/2; Nakabayashi [0017]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nakabayashi (US 20220399297 A1) in view of Takami et al. (JP 2014192363 A) and in further view of Nakamura et al. (US 20200315013 A1)
Regarding Claim 4 – Nakabayashi in view of Takami teaches the terminal structure according to claim 1, but fails to disclose wherein the side surface of the second wiring layer is curved and recessed into the second wiring layer with an arcuate cross section.
Nakamura teaches the side surface of the second wiring layer is curved and recessed into the second wiring layer with an arcuate cross section (Fig 3A; Nakamura [0047] states “a side surface 412 of the conductor pattern (41a) is curved toward an inner side of the conductor pattern (41a), and the conductor pattern (41a) has a concave surface as the side surface 412. The side surface 412… is entirely curved inward”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Nakabayashi in view of Takami with the side surface of the second wiring layer is curved and recessed into the second wiring layer with an arcuate cross section as taught by Nakamura because Nakamura explains that compared to flat surfaces, curved side surfaces increase contact area and improve adhesion strength, making interfacial peeling unlikely.
Allowable Subject Matter
Claims 2-3 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ADITYA SHARMA/ Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847