Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species III Fig. 11), Sub-species A, claims 1-20 in the reply filed on 07/27/2026 is acknowledged. The traversal for Species I (Fig. 3), Species II (Fig. 10) are found persuasive and therefore considered as a same species and all claims are examined based on applicant’s above election.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially createddoctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321(d)may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign aterminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1, 15 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 13 of US patent application 18/620/469 and Dutta et al (US 2021/0134883 A1). Although the conflicting claims are not identical, they are not patentably distinct from each other.
Regarding claim 1: A semiconductor device comprising:
a substrate including a cell region, a peripheral region, and a boundary region therebetween;
a first lower insulating layer disposed on the cell region and extending onto the boundary region and the peripheral region;
a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the boundary region and the peripheral region; data storage patterns disposed on the second lower insulating layer on the cell region;
a cell insulating layer disposed on the second lower insulating layer on the cell region and the boundary region and covering the data storage patterns;
a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer; and
a buffer insulating layer disposed on the cell insulating layer on the boundary region.
Claim 1 of ‘7102: 1. A semiconductor device comprising:
a substrate including a cell region and a peripheral region;
a first lower insulating layer on the cell region and extending onto the peripheral region;
a second lower insulating layer on the cell region and on the first lower insulating layer and extending onto the first lower insulating layer on the peripheral region;
data storage patterns on the second lower insulating layer on the cell region;
a cell insulating layer on the cell region and on the second lower insulating layer and covering the data storage patterns; and
a peripheral insulating layer on the peripheral region and on the second lower insulating layer and including a material different from materials of the cell insulating layer,
wherein a thickness of the second lower insulating layer on the peripheral region is smaller than a maximum thickness of the second lower insulating layer on the cell region.
Claim 1 of ‘7102 does not teach a buffer insulating layer disposed on the cell insulating layer on the boundary region.
Dutta teaches in Fig. 8 about a buffer insulating layer 602/504 disposed on the cell insulating layer 310 on the boundary region.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Dutta’s teachings to ‘7102 semiconductor device to have the feature as claimed to further protect the cell region while making electrical contacts to avoid shot circuits to the surroundings.
Regarding claim 15: A semiconductor device comprising:
a substrate including a cell region, a peripheral region, and a boundary region therebetween;
a first lower insulating layer disposed on the cell region and extending onto the peripheral region;
a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the boundary region and the peripheral region; data storage patterns disposed on the second lower insulating layer on the cell region;
lower electrode contacts penetrating the first lower insulating layer and the second lower insulating layer on the cell region and connected to the data storage patterns, respectively;
a cell insulating layer disposed on the second lower insulating layer on the cell region and the boundary region and covering the data storage patterns;
a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer;
a peripheral conductive contact disposed in the peripheral insulating layer and penetrating the first lower insulating layer and the second lower insulating layer on the peripheral region; and
a buffer insulating layer disposed on the cell insulating layer on the boundary region.
Claim 13 of ‘7102: A semiconductor device comprising:
a substrate including a cell region and a peripheral region;
a first lower insulating layer on the cell region and extending onto the peripheral region;
a second lower insulating layer on the cell region and on the first lower insulating layer and extending onto the first lower insulating layer on the peripheral region;
data storage patterns on the second lower insulating layer on the cell region;
lower electrode contacts on the cell region, penetrating the first lower insulating layer and the second lower insulating layer, and connected to the data storage patterns, respectively;
a cell insulating layer on the second lower insulating layer on the cell region and covering the data storage patterns;
a peripheral insulating layer on the peripheral region and on the second lower insulating layer and including a material different from materials of the cell insulating layer; and
a peripheral conductive contact in the peripheral insulating layer and penetrating the first lower insulating layer and the second lower insulating layer on the peripheral region,
wherein an upper surface of the second lower insulating layer on the peripheral region is at a lower height than an uppermost surface of the second lower insulating layer on the cell region, and the peripheral insulating layer is in contact with a side surface of the cell insulating layer and the upper surface of the second lower insulating layer on the peripheral region.
Claim 13 of ‘7102 does not teach a buffer insulating layer disposed on the cell insulating layer on the boundary region.
Dutta teaches in Fig. 8 about a buffer insulating layer 602/504 disposed on the cell insulating layer 310 on the boundary region.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Dutta’s teachings to ‘7102 semiconductor device to have the feature as claimed to further protect the cell region while making electrical contacts to avoid shot circuits to the surroundings.
Claims 1, 15 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 13 of US patent application 19/265035 and Dutta et al (US 2021/0134883 A1). Although the conflicting claims are not identical, they are not patentably distinct from each other.
Claim 15 of ‘0298: A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a first lower insulating layer disposed on the cell region and extended to the peripheral region;
a second lower insulating layer disposed on the first lower insulating layer on the cell region and extended to the first lower insulating layer on the peripheral region;
data storage patterns disposed on the second lower insulating layer on the cell region and spaced apart from each other in a first direction and a second direction, which are parallel to a top surface of the substrate and are not parallel to each other;
cell conductive lines disposed on the data storage patterns, respectively, which are spaced apart from each other in the first direction;
a cell insulating layer disposed on the second lower insulating layer on the cell region to cover the data storage patterns;
a capping insulating layer interposed between a side surface of each of the data storage patterns and the cell insulating layer;
a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region, the peripheral insulating layer comprising a material different from the cell insulating layer; and
a peripheral conductive contact disposed in the peripheral insulating layer to penetrate the first and second lower insulating layers on the peripheral region, wherein each of the cell conductive lines comprises a first portion adjacent to each of the data storage patterns and a second portion on the first portion, and wherein the capping insulating layer is extended to a side surface of the first portion.
Claim 13 of ‘0298 does not teach a buffer insulating layer disposed on the cell insulating layer on the boundary region.
Dutta teaches in Fig. 8 about a buffer insulating layer 602/504 disposed on the cell insulating layer 310 on the boundary region.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Dutta’s teachings to ‘7102 semiconductor device to have the feature as claimed to further protect the cell region while making electrical contacts to avoid shot circuits to the surroundings.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-11, 15 are rejected under 35 U.S.C. 103 as being obvious over Dutta et al (US 2021/0134883 A1) in view of Peng et al (US 2020/0106007 A1).
Regarding claims 15, 1: Dutta teaches in Fig. 8 about a semiconductor device comprising:
PNG
media_image1.png
672
680
media_image1.png
Greyscale
a substrate including a cell region 124, a peripheral region 122, and a boundary region 125 therebetween (Fig. 1);
a first lower insulating layer 126 disposed on the cell region and extending onto the peripheral region;
a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the boundary region and the peripheral region;
data storage patterns 304 disposed on the second lower insulating layer on the cell region;
lower electrode contacts 128 penetrating the first lower insulating layer and the second lower insulating layer on the cell region and connected to the data storage patterns, respectively;
a cell insulating layer 310 disposed on the second lower insulating layer on the cell region and the boundary region and covering the data storage patterns (Fig. 3);
a peripheral insulating layer 402 disposed on the second lower insulating layer on the peripheral region and including a material [0044] different from that of the cell insulating layer [0043];
a peripheral conductive contact (808+406) disposed in the peripheral insulating layer and penetrating the first lower insulating layer and the second lower insulating layer on the peripheral region; and
a buffer insulating layer 602/504 disposed on the cell insulating layer 310 on the boundary region.
Dutta does not explicitly show a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the boundary region and the peripheral region.
However Dutta teaches in [0032] the top portion 126 of the metallization stack 102 may comprise one or more dielectric materials and the thicker dielectric cap layer 126 allows for an MRAM pillar to be formed with a taller bottom electrode contact than conventional MRAM devices, and further prevents/reduces the risk of metal migration from underlying metal lines.
Peng further teaches in Fig. 2 about a first lower insulating layer 120/130 disposed on the cell region and extending onto the peripheral region;
a second lower insulating layer 130/140’ disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the boundary region and the peripheral region and lower electrode contacts 150 penetrating the first lower insulating layer and the second lower insulating layer on the cell region and connected to the data storage pattern s (162+172+182), respectively.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Peng’s teachings to Dutta’s semiconductor device to have multilayer insulating layers around the electrode contacts for better connection to avoid leakage and short circuits.
Regarding claim 2: Dutta teaches in Fig. 8 further comprising an upper insulating layer 502 interposed between the cell insulating layer 310 and the buffer insulating layer 602 on the boundary region and extending onto the cell insulating layer on the cell region.
Regarding claim 6: Dutta teaches in Fig. 8 further comprising first cell conductive lines 506 + 302 respectively disposed on the data storage patterns in the cell region and penetrating the upper insulating layer 502 and the cell insulating layer on the cell region, wherein the first cell conductive lines are connected to the data storage patterns 304, respectively.
Regarding claim 8: Peng teaches in Fig. 2 wherein the second lower insulating layer 140’ on the cell region has an upper surface recessed toward the substrate between the data storage patterns (180/182), wherein the second lower insulating layer on the boundary region has an upper surface that is recessed toward the substrate, and wherein the recessed upper surface of the second lower insulating layer on the boundary region is positioned at a lower height than the recessed upper surface of the second lower insulating layer on the cell region.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Peng’s teachings to Dutta’s semiconductor device to reduce parasitic capacitance, improve photolithography alignment and provide reliable electrical isolation.
Regarding claim 9: Peng teaches in Fig. 2 further comprising lower electrode contacts 150 disposed in the second lower insulating layer 140’ on the cell region (CR) and connected to the data storage patterns (180/182), respectively, wherein an upper surface of the second lower insulating layer on the cell region is positioned at the same height as upper surfaces of the lower electrode contacts.
Regarding claim 10: Dutta teaches in Fig. 8 wherein the buffer insulating layer 504 extends onto the peripheral insulating layer 402 on the peripheral region.
Regarding claims 7, 11: Dutta teaches in Fig. 8 further comprising: first cell conductive lines 506 + 302 respectively disposed on the data storage patterns 304 in the cell region, penetrating the upper insulating layer and the cell insulating layer on the cell region, and respectively connected to the data storage patterns; and a peripheral conductive line 406 penetrating the buffer insulating layer on the peripheral region and penetrating an upper portion of the peripheral insulating layer, wherein a difference between a height of an upper surface of the peripheral conductive line and a height of upper surfaces of the first cell conductive lines is within 15 nm.
Dutta in view of Peng does not explicitly talk about wherein a difference between a height of an upper surface of the peripheral conductive line and a height of upper surfaces of the first cell conductive lines is within 15 nm.
However Dutta teaches in [0025] the fabrication processes generally deposit a dielectric cap layer having a thickness/height in the range of 10 nm to 100 nm.
Thus, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to have the feature as claimed with routine experiment and optimization by following fabrication process capabilities since the thickness of the dielectric layers region are critical and the height/length of the conductive lines and contacts would be within the process parameters.
is formed is critical in order to control parasitic effect according to the teaching of Loubet ([0004]). In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claims 3, 12, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “wherein the upper insulating layer on the boundary region has an upper surface recessed toward the substrate, and wherein the recessed upper surface of the upper insulating layer on the boundary region is positioned at a lower height than an uppermost surface of the upper insulating layer on the cell region” in combination with other limitations as a whole.
Claims 4-5, 13-14, 17-20 are also allowable being dependent on allowable claims 3, 12, 16
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Prosecution Insights