Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 08/04/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Foster, U.S. Patent 6,818,973.
Foster shows the invention as claimed including an electronic device, comprising:
Peripheral first leads (180 or 80), each peripheral first lead having lateral sides, a top side, and a bottom side (see, for example, fig. 6);
Interior second leads 68, each interior second lead having lateral sides, a top side, and a bottom side;
A first package structure (for example, 94) extending on the top sides of the peripheral first leads, the top sides of the interior second leads, upper first portions of the lateral sides of the interior second leads, and the first package structure exposing one lateral side of each of the peripheral first leads; and
A second package structure (see portion of package structure 94 between peripheral first leads and interior second leads) extending laterally around lower second portions of the lateral sides of the interior second leads, the second package structure exposing the bottom side of each of the peripheral first leads, the second package structure exposing one lateral side of each of the peripheral first leads, the second package structure exposing the bottom side of each of the interior second leads (see figs. 3-6 and col. 3-line 61 to col. 8-line 13).
With respect to dependent claim 2, note that Foster discloses a semiconductor die (for example, 86) electrically connected to one of the peripheral first leads and to one of the interior second leads.
As to dependent claim 3, note that Foster discloses wherein the peripheral first leads and the interior second leads are of the same material (see fig. 6).
Concerning dependent claim 4, note that Foster discloses wherein the second package structure extends to a bottom side of the electronic device (again, see fig. 6).
With respect to dependent claim 8, note that Foster discloses wherein a semiconductor die is attached to one of the interior second leads and the one of the interior second leads is configured to extract heat from the semiconductor die (see col. 10-lines 22-35).
As to independent claim 10, note that Foster additionally discloses a circuit board including a conductive feature (see, for example, col. 12-line 63 to col. 13-line 20).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster, U.S. Patent 6,818,973 in view of Dlugokecki, US Patent 5,318,926.
Foster is applied as above and additionally discloses where the package structures comprise encapsulant materials but does not expressly disclose where the first and second package structures include epoxy molding compound. Dlugokecki discloses encapsulant materials comprising epoxy molding compounds (see col. 4-line 51 to col. 5-line 13). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Foster so as to include epoxy molding compounds as encapsulant materials since Dlugokecki shows epoxy materials to be suitable encapsulation materials.
Claim(s) 6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster, U.S. Patent 6,818,973 in view of Juskey et al., U.S. Patent 5,371,404.
Foster is applied as above but does not expressly disclose where the semiconductor die is a semiconductor flip-chip. Juskey et al. discloses where a semiconductor die 16 is flip chip bonded to the remaining structure (see col. 3-lines 47-65). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Foster so as to comprise a semiconductor flip-chip because Juskey shows this as a suitable method in which semiconductor dies are formed in packaging structures.
Claim(s) 7 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster, U.S. Patent 6,818,973 in view of Kummerl et al., US Patent 12,364,052.
Foster is applied as above but does not expressly disclose a wire bond connected between a semiconductor die and one of the interior second leads. Kummerl et al. discloses a wire bond 420 connected between a semiconductor die 416 and a die pad 412 which is an interior lead (see, for example, fig. 4 and col. 5, lines 20-43). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Foster so as to comprise the claimed wire bond as suggested by Kummerl et al. because the claimed wire bond is shown by Kummerl et al. to be a suitable method of electrical connection.
Claim(s) 9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster, U.S. Patent 6,818,973.
Foster is applied as above but does not expressly disclose the particular configuration of the interior second leads. However, a prima facie case of obviousness still exists because the configuration of the claimed interior second leads is a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ho et al., US 2026/0123456 discloses a semiconductor die that is wire bonded to peripheral leads (see, for example, fig. 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
October 13, 2026
Prosecution Insights