DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/01/2025 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The newly-amended title is considered sufficiently descriptive; the Objection(s) to the title in the Final Office Action mailed 10/01/2025 has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. PG Pub No US2019/0378857A1) (of record).
Regarding claim 11, Lee teaches a memory device (200) fig. 11A [0093, 0099] comprising:
a peripheral circuit structure (PERI comprising 220) fig. 11A [0040, 0026, 0095, 0100] including interconnection structures (280) fig. 11A [0098] coupled to a peripheral circuit (comprising 220);
a cell stack structure (GS) [0039, 0042] including a plurality of gate conductive patterns (130s comprising 132s) [0042, 0064], the cell stack structure (GS) stacked on the peripheral circuit structure (PERI comprising 290), wherein each of the plurality of gate conductive patterns (132s of 130s) [0064] includes a first horizontal part (H1) and a second horizontal part (H2), the first horizontal part (H1) and the second horizontal part (H2) extending from a cell region (I comprising CH’s) [0039-0040] to a contact region (II comprising 170s) [0039-0040, 0045] (see fig. 4 for labels I-II), and a third horizontal part (H3) connected to one (right) end of the first horizontal part (H1) and one end of the second horizontal part (H2), the third horizontal part (H3) connected to a corresponding gate contact structure (170-II) among the plurality of gate contact structures (170s) (see annotated fig. 5 of Lee below);
each of a plurality of gate contact structures (respective 170) connecting one of the plurality of gate conductive patterns (respective 130) to one of the interconnection structures (respective 280);
a continuous first insulating pattern (an individual one of 135 of second-from-lowermost 135’s) fig. 11A [0045] (see also annotated fig. 5 of Lee below) disposed between a first horizontal part (H1) and a second horizontal part (H2) of a first gate conductive pattern (second-from-lowermost 132) fig. 11A [0064] among the plurality of gate conductive patterns (130s comprising 132s); and
wherein at least two of the plurality of gate contact structures (170 may represent a double-layer [0060], with individual of these layers considered as different ‘gate contact structures’; because 170 comprises two-layers [0060], one 170 element comprises two gate contact structures) fig. 4 [0064, 0060] extend through and are surrounded by the first insulating pattern (an individual one of 135 of second-from-lowermost 135’s) (see fig. 11A).
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Annotated fig. 11A and 5 of Lee designating respective horizontal parts (H1-H3) and contacts (170)
Regarding claim 12, Lee teaches a memory device (200) fig. 11A [0093, 0099] of claim 11. Lee also teaches wherein the plurality of gate conductive patterns (132s of 130) [0042, 0064] are arranged to be sequentially stacked to form a stepped structure (see fig. 11A) wherein lengths of the first (H1) and second (H2) horizontal parts of each gate conductive pattern (132) located further from the peripheral circuit structure (PERI below stack) are shorter than lengths of the first (H1) and second (H2) horizontal parts of each gate conductive pattern (130) located closer to the peripheral circuit structure (PERI) (see fig. 11A staircase structure).
Regarding claim 13, Lee teaches a memory device (200) fig. 11A [0093, 0099] of claim 11. Lee also teaches wherein each of the plurality of gate contact structures (170) fig. 11A [0059] penetrates a region between the first horizontal part (H1) and the second horizontal part (H2) of at least one gate conductive pattern (lower 130) disposed under a corresponding gate conductive pattern (upper 130) among the plurality of gate conductive patterns (132s of 130s) [0064].
Regarding claim 14, Lee teaches a memory device (200) fig. 11A [0093, 0099] of claim 11. Lee also teaches wherein each of the plurality of gate contact structures (170) fig. 11A [0059] extends vertically in an external (above) region of at least one gate conductive pattern (130) fig. 11A [0063] disposed above a corresponding gate conductive pattern (respective 132 of 130) among the plurality of gate conductive patterns (130s comprising 132s) [0042, 0064].
Allowable Subject Matter
Claims 1-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 is allowed because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “the first gate conductive pattern surrounds an only single insulating pattern, and the second gate conductive pattern surrounds an only single insulating pattern” in the context of claim 1. Claims 2-10 are also allowed by virtue of their dependency on claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 11-14 have been considered but are rendered largely-moot by a reinterpretation a “gate contact structure” 170 in Lee to correspond to an individual 170-layer. Because [0060] explicitly discloses that “contact plugs 170 may be formed having a double-layer” – 170 has been considered as a representation of two gate contact ‘structures’ (layers); one 170 element comprises two gate contact structures, both surrounded by a single, continuous 135 element.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant because they disclose contact structures penetrating a gate-stack.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/15/2026
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892