Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim17 objected to because of the following informalities: the body of the claim teachers the limitation “ …; and bonding the second bonding pad with each of an the upper surface of the first bonding pad and the upper surface of the first through electrode”.
Claim12 is also objected to because of the following informalities: the body of the claim teachers the limitation “ …an top surface …”
Appropriate correction is required for all those claims.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/31/2024 , and 07/23/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: are using for example the term “comprises or comprising ”. The claim used a wherein close for the forming step after the term “pad” ( see body of the claim 12 stating : The method of claim 11, wherein forming the first bonding pad: forming…) which should be followed by specific terms such as “ comprising or comprises” in order to make some sense.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7,11-14,18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al, US 20190139785 A1.
PNG
media_image1.png
556
588
media_image1.png
Greyscale
Pertaining to claim 1, Lee teaches ( see figs.2A,4A-4H for example )
A method for manufacturing a semiconductor chip, the method comprising: forming a via insulating layer[205] ( see para 0030) and a through electrode[130/220] in a substrate[100], the through electrode[230/220/210] penetrating the substrate, and the via insulating layer[205] disposed between the through electrode [230/220/210] and the substrate[100]; forming a pad insulating layer [120] on a first surface of the substrate[100]; forming a recess [125] in the pad insulating layer[120] to expose a sidewall of an upper portion of the through electrode ( see fig.4F); forming a preliminary bonding pad [311/312] in the recess [125] and on the pad insulating layer[205]; and performing planarization process( see fig.4H) ( see also para 0057) on the preliminary bonding pad to form a bonding pad, the bonding pad exposing an upper surface of the through electrode[ 230/220/210] and a top surface of the pad insulating layer[120], wherein the bonding pad [310/320] is in contact with the sidewall of the upper portion of the through electrode[230/220/210].
Pertaining to claim 2, Lee teaches ( see figs.2A,4A-4H )The method of claim 1, wherein forming the recess [125] comprises: etching a portion of the pad insulating layer[120]; and etching a portion of the via insulating layer[205] to expose the sidewall of the upper portion of the through electrode[230/220/210].
Pertaining to claim 3, Lee teaches ( see figs.2A,4A-4H )The method of claim 1, wherein an upper surface of the via insulating layer[205] is disposed at a lower level than the upper surface of the through electrode[230/220/210], after forming the recess.
Pertaining to claim 4, Lee teaches ( see fig.2A )The method of claim 1, wherein the bonding pad [310/320] has a ring-shape[310], in a plan view.
Pertaining to claim 5, Lee teaches ( see fig.4A-4H )The method of claim 1, wherein the forming the preliminary bonding pad comprises: forming a conductive seed layer [311] on a bottom surface and a sidewall of the recess[125], the conductive seed layer being in contact with the sidewall of upper portion of the through electrode[230/220/210]; and forming a conductive core layer[312] on the seed pad [311] to fill the recess[125].
Pertaining to claim 6, Lee teaches ( see fig.4H )The method of claim 5, wherein an upper surface of the conductive seed layer [311] and an upper surface of the conductive core layer[312] are disposed at substantially a same level, after performing the planarization process ( see fig.4H).
Pertaining to claim 7, Lee teaches ( see fig.4A-4H )The method of claim 5, wherein forming the through electrode[230/220/210] comprises: forming a via hole[250] in the substrate[100] to penetrate a second surface[100b] of the substrate; forming a conductive barrier layer [210] on a sidewall of the via hole[205]; and forming a conductive plug[230] on the conductive barrier layer[210] to fill the via hole[250].
Pertaining to claim 11, Lee teaches ( see figs.2A,4A-4H for example ) a method for manufacturing a semiconductor apparatus, the method comprising: forming a via insulating layer[205] and a through electrode [230/220/210] in a first substrate[100], the first through electrode[[230/220/210] penetrating the substrate[100], and the via insulating layer[205] disposed between the first through electrode[230/220/210] and the first substrate[100]; forming a pad insulating layer[120] on a first surface of the first substrate[100]; forming a recess[125] in the pad insulating layer [120] to expose a sidewall of an upper portion of the through electrode [230/220/210] ; and forming a first bonding pad[311/312] in the recess [125] to cover the sidewall of the upper portion of the first through electrode [230/220/210] and an upper surface of the via insulating layer[205], wherein the first bonding pad[310/320] exposes an upper surface of the first through electrode [230/220/210], and wherein the first bonding pad[310/320] has a ring-shape[310], in a plan view ( see fig.2A)
Pertaining to claim 12, Lee teaches ( see figs.2A,4A-4H for example ) The method of claim 11, wherein forming the first bonding pad: forming a preliminary bonding pad[311/312] in the recess[125] and on a top surface of the pad insulating layer[120]; and planarizing the preliminary bonding pad to form the first bonding pad ( see para 0054), until exposing the upper surface of the first through electrode[230/220/210] and an top surface of the pad insulating layer[120].
Pertaining to claim 13, Lee teaches ( see figs.2A,4A-4H for example ) The method of claim 11, wherein the forming the recess[125] comprises: removing a portion of the pad insulating layer[120] and a portion of the via insulating layer[205].
Pertaining to claim 14, Lee teaches ( see figs.2A,4A-4H for example ) The method of claim 11, wherein forming the first bonding pad comprises: forming a conductive seed layer[311] on a bottom surface and a sidewall of the recess[125]; and forming a conductive core layer[312] on the seed pad to fill the recess[125], wherein the conductive seed layer [311]is disposed between the sidewall of upper portion of the first through electrode and an inner circumferential surface the conductive core layer[312] and is in contact with the sidewall of upper portion of the first through electrode[230/220/210].
Pertaining to claim 18, Lee teaches ( see figs.2A,4A-4H for example ) A method for manufacturing a semiconductor chip, the method comprising: forming a via hole [250] penetrate an lower surface of a semiconductor substrate[100]; forming a via insulating layer[205] ( see para 0030) on a sidewall of the via hole[250]; forming a through electrode [230/220/210] on an inner sidewall of the via insulating layer[205] to fill the via hole[250], the through electrode via [230/220/210] comprises a conductive plug[230] and a conductive barrier layer[210] on a sidewall of the conductive plug[230]; forming a wiring structure [110] on the lower surface of the semiconductor substrate[110]; forming an pad insulating layer[120] on an upper surface of the semiconductor substrate[100]; performing an etching process on the pad insulating layer[120] to form a recess[125] in the pad insulating layer[120], wherein performing an etching process comprises removing a portion of the via insulating layer[205] to expose a sidewall of an upper portion of the through electrode [230/220/210]; forming a preliminary bonding pad [311/312] in the recess [125] and on a top surface of the pad insulating layer[120]; and planarizing ( see fig.4H) ( see also para 0057) the preliminary bonding pad [311/312] to form a bonding pad[310/320], the bonding pad[310/320] exposing an upper surface of the through electrode [230/220/210] and the top surface of the pad insulating layer[120], wherein the bonding pad [310/320] is in contact with the sidewall of the upper portion of the through electrode[230/220/210] and covers an upper surface of the via insulating layer [205].
Pertaining to claim 19, Lee teaches ( see figs.2A,4A-4H for example )The method of claim 18, further comprising: removing a portion of the semiconductor substrate [100] such that an end portion of the through electrode[230/220/210] protrudes from a second surface[100b] of the first substrate[100], wherein forming the pad insulating layer [120] comprises forming a first insulating layer covering the end portion of the through electrode [230/220/210], and wherein the via insulating layer[205] is disposed between the first insulating layer [120] and the through electrode[230/220/210], before forming the recess[125] ( see para 0050).
Pertaining to claim 20, Lee teaches ( see figs.2A,4A-4H for example )The method of claim 19, wherein the end portion of the through electrode[230/220/210] comprises the upper portion of the through electrode[230/220/210].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20190139785 A1 in view of Tsai et al, US 20110304026 A1.
Pertaining to claim 8, Lee teaches the method of claim 7, but silent wherein a grain size of the conductive plug is greater than a grain size of the conductive core layer.
However, in the same field if endeavor, Tsai teaches wherein a grain size of the conductive plug [84] is different than a grain size of the conductive core layer[40]. In view of Tsai , the ordinary artisan would have recognized the grain size of the different layers to be a result effective variable affecting the effectiveness of the bonding contact between to the two layers . Thus, it would have been obvious to for one layer grain size to be greater or larger than the other one, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Allowable Subject Matter
Claims 9-10, 15-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Lee et al, US 20190139785 A1teaches the limitation of claim1, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 9 including " wherein a distance between an inner circumference and an outer circumference of an upper surface of the bonding pad is about 0.5 to about 10 times a horizontal width of the upper surface of the through electrode.” in combination with the remaining limitations of the claim.
it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 10 including " wherein forming the pad insulating layer comprises: forming a first insulating layer on the first surface of the substrate; forming a second insulating layer on the first insulating layer; and forming a third insulating layer on the second insulating layer, wherein the second insulating layer comprises a different material from a material of the first insulating layer and a material of the third insulating layer.” in combination with the remaining limitations of the claim.
it does not also teach or suggest, singularly or in combination, at least the limitations of the dependent claim 15 including " further comprising: providing a second semiconductor chip on the first substrate, the second semiconductor chip comprising a second substrate, a second bonding pad on a lower surface of the second substrate, and a second through electrode penetrating the second semiconductor substrate and connected to the second bonding pad; and bonding the second bonding pad with the first bonding pad.” in combination with the remaining limitations of the claim.
it does not finally teach or suggest, singularly or in combination, at least the limitations of the dependent claim 17 including " further comprising: providing a second semiconductor chip on the first substrate, the second semiconductor chip comprising a second substrate and a second bonding pad on a lower surface of the second substrate; and bonding the second bonding pad with each of an the upper surface of the first bonding pad and the upper surface of the first through electrode.” in combination with the remaining limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAMADOU L DIALLO whose telephone number is (571)270-5449. The examiner can normally be reached M-F: 9:00AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FERNANDO TOLEDO can be reached on (571)272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897