DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on May 31, 2024 has been considered by the examiner.
Claim Objections
Claims objected to because of the following informalities:
Claims 1, 8, and 11: Claims include language such as, “a first one of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors has a first threshold voltage distribution.” A singular transistor cannot have a distribution of voltage thresholds. In the interest of compact prosecution, this language will be read as, “having a voltage threshold within a first threshold voltage distribution.” Similar modifications will be read for each of the second, third, and fourth ground selection transistors.
Claim 7 and Claim 18: Claim reads, “each of the plurality of cell strings further includes a common ground selection transistor connected in series to each other…” More than two ground selection transistors cannot be both connected serially and also each connected to all others. The phrase ‘to each other’ will be omitted for the purposes of compact prosecution.
Claim 8: Unclear language. Claim 8 describes the semiconductor device as in claim 7, wherein, “based on the common ground selection transistor in each of the plurality of cell strings, the plurality of cell strings provide…” ‘Based on’ is incorrect terminology.
Claim 8: Claim 8 further discloses, “the plurality of cell strings provide a plurality of common ground selection transistors having a same threshold voltage distribution.” The same threshold voltage distribution as what? This sentence will be read as, “common ground selection transistors, each having a voltage threshold within the same threshold voltage distribution.”
Claim 20: Improper punctuation. Claim includes a stray period in the middle of the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 10,971,238 B2 to Kanamori, et al. (hereafter Kanamori).
Regarding Independent Claim 1, Kanamori discloses a semiconductor device comprising:
a substrate (A semiconductor structure built on a substrate: Kanamori, col.5:35-38);
a plurality of cell strings disposed perpendicular to an upper surface of the substrate (Cell strings formed normal to the substrate: Kanamori, Figure 2); and
a bit line connected to at least six of the plurality of cell strings (A bit line connected to at least six cell strings: Kanamori, col.13:10-16),
wherein each of the plurality of cell strings includes
a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate (Memory cells connected in series: Kanamori, Figure 3),
a first ground selection transistor to a fourth ground selection transistor (Disclosing six ground select transistors on a string, necessitating at least four ground select transistors: Kanamori, col.13:21-23; See also, Memory strings comprising two or four ground select transistors: Kanamori, col.10:66-11:1) connected in series to each other between the plurality of memory cells and the substrate (Ground select transistors connected between cells and substrate: Kanamori, Figure 3), and
a string selection transistor between the plurality of memory cells and the bit line (String select transistors SST located between memory cells and bit line: Kanamori, Figure 2),
based on the string selection transistor and the first ground selection transistor to the fourth ground selection transistor in each of the plurality of cell strings (General memory cell string: Kanamori, Figure 13),
the plurality of cell strings provide
a plurality of string selection transistors (String select transistors SST: Kanamori, Figure 13),
a plurality of first ground selection transistors (First ground select transistors GST1: Kanamori, Figure 13),
a plurality of second ground selection transistors (Second ground select transistors GST2: Kanamori, Figure 13),
a plurality of third ground selection transistors (Third ground select transistors GST3: Kanamori, Figure 13), and
a plurality of fourth ground selection transistors (Fourth ground select transistors GST4: Kanamori, Figure 13),
the plurality of string selection transistors of the plurality of cell strings are electrically separated from each other (The plurality of string select transistors on the strings being electrically separated: Kanamori, Figure 13),
the plurality of first ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of first ground select transistors configured to be operated in common: Kanamori, Figure 13),
the plurality of second ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of second ground select transistors configured to be operated in common: Kanamori, Figure 13),
the plurality of third ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of third ground select transistors configured to be operated in common: Kanamori, Figure 13),
the plurality of fourth ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of fourth ground select transistors configured to be operated in common: Kanamori, Figure 13),
a first one of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors has a first threshold voltage distribution (A first one of the first ground select transistors having a first threshold voltage distribution Vth1: Kanamori, Figure 20),
a second one of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors has a second threshold voltage distribution (A second of the first ground select transistors has a second threshold voltage Vth2: Kanamori, Figure 20), and
the second threshold voltage distribution is different from the first threshold voltage distribution (The first and second threshold voltages being different: Kanamori, col.18:39-45).
Regarding Claim 2, Kanamori discloses the semiconductor device of claim 1, wherein
at least two of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors have the first threshold voltage distribution (At least two of the first ground select transistors being programmed with the first threshold voltage distribution: Kanamori, Figure 20).
Regarding Claim 3, Kanamori discloses the semiconductor device of claim 1, further comprising:
a first ground selection line (Ground selection line SGL1a: Kanamori, Figure 13),
a second ground selection line (Ground selection line SGL1b: Kanamori, Figure 13),
a third ground selection line (Ground selection line SGL1c: Kanamori, Figure 13), and
a fourth ground selection line (Ground selection line SGL1d: Kanamori, Figure 13)
that are vertically stacked on the substrate (Ground selection lines stacked vertically above the substrate: Kanamori, Figure 13),
wherein each of the first ground selection line, the second ground selection line, the third ground selection line, and the fourth ground selection line is a single conductive pattern extending in a first direction (Each of the ground selection lines being independent conductive patterns: Kanamori, Figure 13),
the first direction is parallel to the upper surface of the substrate (The ground selection lines being parallel to each other and to the substrate: Kanamori, Figure 13), and
the first ground selection line, the second ground selection line, the third ground selection line, and the fourth ground selection line are connected to the plurality of first ground selection transistors, the plurality of second ground selection transistors, the plurality of third ground selection transistors, and the plurality of fourth ground selection transistors, respectively (Each of the first through fourth ground selection lines GSL1a-GSL1d connected to the first through fourth ground select transistors GST1-GST4 at each of the plurality of memory cell lines: Kanamori, Figure 13).
Regarding Claim 4, Kanamori discloses the semiconductor device of claim 3, further comprising:
a first separation structure and a second separation structure on the substrate and extending in the first direction (At least two separation structures extending in the first direction: Kanamori, col.12:6-10 and Kanamori, Figure 9),
wherein the first ground selection line, the second ground selection line, the third ground selection line, and the fourth ground selection line are between the first separation structure and the second separation structure (A separation structure located above the GSL structure: Kanamori, col.12:10-17; Ground selection lines are further necessarily electrically separated from the base substrate).
Regarding Claim 5, Kanamori discloses the semiconductor device of claim 4, further comprising:
a plurality of string selection lines spaced apart from each other with a regular interval (The string selection lines 1-6 being spaced at regular intervals: Kanamori, Figure 13) between the first separation structure and the second separation structure (The string selection lines being separated from the the memory cells and bit line by insulating structures: Kanamori, Figure 13),
wherein the plurality of string selection lines are positioned at a same level from the substrate (Each of the string selection lines SSL1-6 being located at the same level: Kanamori, Figure 13).
Regarding Claim 6, Kanamori discloses the semiconductor device of claim 5, wherein
a width of the first ground selection line, a width of the second ground selection line, a width of the third ground selection line, and a width of the fourth ground selection line each are greater than a sum of widths of at least six of the plurality of string selection lines (The described structure is merely the expected result of standard memory array construction. Ground select lines and word lines extend in the first direction and extend the full width of the block. In this same space, in this direction, multiple coplanar string select lines exist and are separated by each other by insulating structures. The sum of the widths of the string select lines therefore must equal the width of any given ground select line minus the combined widths of any insulating structures: Kanamori, Figure 8).
Regarding Claim 7, Kanamori discloses the semiconductor device of claim 1, wherein
each of the plurality of cell strings further includes a common ground selection transistor connected in series to each other between the substrate and the first ground selection transistor (Disclosing six ground select transistors between the substrate and the first level of memory cells, designating either of the first two ground select transistors as a ‘common ground selection transistor’ leaves the remaining ground select transistors in the same configuration previously described: Kanamori, Figure 13).
Regarding Claim 8, Kanamori discloses the semiconductor device of claim 7, wherein
based on the common ground selection transistor in each of the plurality of cell strings, the plurality of cell strings provide a plurality of common ground selection transistors having a same threshold voltage distribution (Kanamori only requires at least one of the ground select transistors have a first threshold voltage, the remaining transistors may all have the second threshold voltage. If the four ground select transistors are chosen from between GSL1b-GSL1f, all GSL1a transistors may considered part of the ‘remaining transistors,’ each programmed to the same voltage Vth2: Kanamori, Figure 13 and col.1:50-54).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,971,238 B2 to Kanamori, et al. (hereafter Kanamori) in view of US 10,276,250 B1 to Wei-Chen Chen, et al. (hereafter Chen).
Regarding Claim 9, Kanamori discloses the semiconductor device of claim 7, wherein
each corresponding cell string of the plurality of cell strings further includes transistors connected in series to each other between the common ground selection transistor and the first ground selection transistor of the corresponding cell string (A dummy transistor is the same as a standard memory cell, except it is used to store data nor typically addressable for the purposes of data storage. Taking the configuration of Kanamori, Figure 13, the first transistor GST1 may be considered the common ground transistor, GST2 has all characteristics of a dummy transistor, and the remaining ground select transistors the equivalent of the claim ground select transistors: Kanamori, Figure 13).
Although Kanamori discloses a common ground select transistor, a dummy transistor, and four individualized ground select transistors, wherein the dummy transistor is located between the common ground transistor and the specialized ground select transistors, it only discloses a single dummy transistor in this configuration. Implementing similar configurations with more than one dummy transistor was previously known in the art, however (See, for instance, Disclosing three dummy transistors located between the common ground select and the memory cells: Chen, Figure 3). Chen teaches the introduction of dummy memory cells are necessary because the common ground select transistor creates a functional edge, leading to disturbance on nearest cells. Introducing multiple dummy cells in this gap helps reduce the disturbance experienced by the array as a whole (Chen, col.2:43-60). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the additional buffer created by having multiple dummy cells, as in Chen, with the multiple gate select transistors or Kanamori, with a reasonable expectation of success. Both inventions are well known in the field of ground select gate management in memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 10 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,971,238 B2 to Kanamori, et al. (hereafter Kanamori) in view of US 2019/0221557 A1 to Kwang-Ho Kim, et al. (hereafter Kim).
Regarding Claim 10, Kanamori discloses the semiconductor device of claim 1, further comprising:
a semiconductor substrate (A semiconductor structure built on a substrate: Kanamori, col.5:35-38), and
a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate (A peripheral circuit bonded on the semiconductor substrate: Kanamori, col.4:7-12 and Kanamori, Figure 1).
Kanamori discloses a memory circuit including a separate memory array and peripheral circuitry, but is silent on how these components are connected. Kim, however, discloses a memory array circuit as in Claim 1, including:
first bonding pads connected to the peripheral circuits (Peripheral circuits connected via bonding pads: Kim, ¶[0168]); and
second bonding pads bonded to the first bonding pads, wherein the second bonding pads are electrically connected to the plurality of cell strings (Additional pads connected to the memory device connecting to the peripheral pads: Kim, ¶[0168]).
Kim teaches this configuration permits a flexible arrangement of device components, specifically allowing control signals from the peripheral components to be reliably passed through to the memory die (Kim, ¶[0180]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible circuit construction of Kim with the ground select gate controlled memory array of Kanamori, with a reasonable expectation of success. Both inventions are well known in the field of semiconductor memory array construction and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 19, Kanamori discloses an electronic system comprising:
a semiconductor device including a peripheral circuit structure and a cell array structure on the peripheral circuit structure (A peripheral circuit bonded on the semiconductor substrate: Kanamori, col.4:7-12 and Kanamori, Figure 1);
wherein the cell array structure includes
a substrate (A semiconductor structure built on a substrate: Kanamori, col.5:35-38),
a plurality of cell strings disposed perpendicular to an upper surface of the substrate (Cell strings formed normal to the substrate: Kanamori, Figure 2), and
a bit line connected to at least six of the plurality of cell strings (A bit line connected to at least six cell strings: Kanamori, col.13:10-16),
each of the plurality of cell strings includes
a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate (Memory cells connected in series: Kanamori, Figure 3),
a first ground selection transistor to a fourth ground selection transistor (Disclosing six ground select transistors on a string, necessitating at least four ground select transistors: Kanamori, col.13:21-23; See also, Memory strings comprising two or four ground select transistors: Kanamori, col.10:66-11:1) connected in series to each other between the plurality of memory cells and the substrate (Ground select transistors connected between cells and substrate: Kanamori, Figure 3), and
a string selection transistor between the plurality of memory cells and the bit line (String select transistors SST located between memory cells and bit line: Kanamori, Figure 2),
based on the string selection transistor and the first ground selection transistor to the fourth ground selection transistor in each of the plurality of cell strings (General memory cell string: Kanamori, Figure 13), the plurality of cell strings provide
a plurality of string selection transistors (String select transistors SST: Kanamori, Figure 13),
a plurality of first ground selection transistors (First ground select transistors GST1: Kanamori, Figure 13),
a plurality of second ground selection transistors (Second ground select transistors GST2: Kanamori, Figure 13),
a plurality of third ground selection transistors (Third ground select transistors GST3: Kanamori, Figure 13), and
a plurality of fourth ground selection transistors (Fourth ground select transistors GST4: Kanamori, Figure 13),
the plurality of string selection transistors of the plurality of cell strings are electrically separated from each other (The plurality of string select transistors on the strings being electrically separated: Kanamori, Figure 13),
the plurality of first ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of first ground select transistors configured to be operated in common: Kanamori, Figure 13),
the plurality of second ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of second ground select transistors configured to be operated in common: Kanamori, Figure 13),
the plurality of third ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of third ground select transistors configured to be operated in common: Kanamori, Figure 13),
the plurality of fourth ground selection transistors in the plurality of cell strings are configured to be controlled in common (The plurality of fourth ground select transistors configured to be operated in common: Kanamori, Figure 13),
a first one of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors has a first threshold voltage distribution (A first one of the first ground select transistors having a first threshold voltage distribution Vth1: Kanamori, Figure 20),
a second one of the plurality of first ground selection transistors to the plurality of fourth ground selection transistors has a second threshold voltage distribution (A second of the first ground select transistors has a second threshold voltage Vth2: Kanamori, Figure 20), and
the second threshold voltage distribution is different from the first threshold voltage distribution (The first and second threshold voltages being different: Kanamori, col.18:39-45).
Kanamori discloses a memory circuit including a separate memory array and peripheral circuitry, but is silent on how these components are connected. Kim, however, discloses a memory array circuit as in Claim 1, wherein:
a controller electrically connected to the semiconductor device through an input/output pad and configured to control the semiconductor device (Peripheral circuits connected via bonding pads: Kim, ¶[0168]).
Kim teaches this configuration permits a flexible arrangement of device components, specifically allowing control signals from the peripheral components to be reliably passed through to the memory die (Kim, ¶[0180]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible circuit construction of Kim with the ground select gate controlled memory array of Kanamori, with a reasonable expectation of success. Both inventions are well known in the field of semiconductor memory array construction and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 20, Kanamori discloses the electronic system of claim 19, wherein
the cell array structure further includes a first separation structure and a second separation structure on the substrate (At least two separation structures extending in the first direction: Kanamori, col.12:6-10 and Kanamori, Figure 9) and
a plurality of string selection lines horizontally spaced apart from each other (The string selection lines 1-6 being spaced at regular intervals: Kanamori, Figure 13) between the first separation structure and the second separation structure (The string selection lines being separated from the the memory cells and bit line by insulating structures: Kanamori, Figure 13),
the first separation structure and the second separation structure extend in a first direction (The separation structures extending in the first direction: Kanamori, Figure 13),
a first ground selection line, a second ground selection line, and a third ground selection line that are vertically stacked on the substrate (Ground selection lines being stacked vertically on the substrate: Kanamori, Figure 13),
wherein the first ground selection line, the second ground selection line, and the third ground selection line are between the first separation structure and the second separation structure (A separation structure located above the GSL structure: Kanamori, col.12:10-17; Ground selection lines are further necessarily electrically separated from the base substrate).
each of the first ground selection line, the second ground selection line, and the third ground selection line is a single conductive pattern extending in the first direction (Each of the first, second, and third ground select transistors controlled in common with the respective ground selection transistors on other lines by a common ground selection line: Kanamori, Figure 13),
the first direction is parallel to the upper surface of the substrate (The first direction being parallel to the substrate: Kanamori, Figure 13), and
the first ground selection line, the second ground selection line, and the third ground selection line are connected to the plurality of first ground selection transistors, the plurality of second ground selection transistors, and the plurality of third ground selection transistors, respectively (Each of the first, second, and third ground select transistors controlled in common with the respective ground selection transistors on other lines by a common ground selection line: Kanamori, Figure 13).
Claim(s) 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,971,238 B2 to Kanamori, et al. (hereafter Kanamori) in view of US 9,412,462 B2 to Byung-Gook Park, et al. (hereafter Park).
Regarding Independent Claim 11, Kanamori discloses a semiconductor device comprising:
a substrate (A semiconductor structure built on a substrate: Kanamori, col.5:35-38);
a plurality of cell strings perpendicular to an upper surface of the substrate (Cell strings formed normal to the substrate: Kanamori, Figure 2); and
a bit line connected to at least six of the plurality of cell strings (A bit line connected to at least six cell strings: Kanamori, col.13:10-16),
wherein each of the plurality of cell strings includes
a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate (Memory cells connected in series: Kanamori, Figure 3),
a plurality of ground selection transistors connected in series to each other between the plurality of memory cells and the substrate (Disclosing six ground select transistors on a string, necessitating at least four ground select transistors: Kanamori, col.13:21-23), and
a string selection transistor between the plurality of memory cells and the bit line (String select transistors SST located between memory cells and bit line: Kanamori, Figure 2),
in each of the plurality of cell strings, the plurality of ground selection transistors include
a first ground selection transistor having a first threshold voltage distribution (A first one of the first ground select transistors having a first threshold voltage distribution Vth1: Kanamori, Figure 20),
a second ground selection transistor having a second threshold voltage distribution (A second of the first ground select transistors has a second threshold voltage Vth2: Kanamori, Figure 20), and
the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are different from each other (The first and second threshold voltages being different: Kanamori, col.18:39-45).
Kanamori does not disclose a set of ground selection transistors having a third threshold voltage distribution different from the first and second threshold voltage distributions. Park, however, discloses a memory array wherein each memory bit line includes multiple string select transistors programmed to different threshold voltage distributions:
A third ground selection transistor having a third threshold voltage distribution (Showing three or more voltage distributions on select transistors: Park, Figure 3a).
Park discloses this arrangement of string select transistor voltage thresholds allow the controller to identify one string or layer among many sharing the same select lines (Park, col.2:1-7). Kanamori discloses the purpose of using two voltage distributions among the ground selection lines serves the same purpose, to electrically separate specific lines from each other even when they are connected to a common ground select line (Kanamori, col.19:15-19). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to extend the memory line isolation method of Kanamori, which arbitrarily stops at two voltage thresholds, as far as desired as described in Park, with a reasonable expectation of success. Both inventions are well known in the field of memory array string selection management and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 12, Kanamori discloses the semiconductor device of claim 11, wherein
the second threshold voltage distribution is greater than the first threshold voltage distribution, and the third threshold voltage distribution is greater than the second threshold voltage distribution (All three voltage threshold distributions are distinct. Therefore, it is inherent one Vth will be less than the other two and one will be greater than the other two).
Regarding Claim 13, Kanamori discloses the semiconductor device of claim 11, wherein
the string selection transistor of each of the plurality of cell strings provides a plurality of string selection transistors (Each memory line including a string select transistor: Kanamori, Figure 13),
the plurality of string selection transistors of the cell strings are electrically separated from each other (The string select transistors electrically isolated from each other: Kanamori, Figure 13), and
the ground selection transistors positioned at a same level in the plurality of cell strings are configured to be commonly controlled (Disclosing six ground select transistors between the substrate and the first level of memory cells, designating either of the first two ground select transistors as a ‘common ground selection transistor’ leaves the remaining ground select transistors in the same configuration previously described: Kanamori, Figure 13).
Regarding Claim 14, Kanamori discloses the semiconductor device of claim 11, further comprising:
a first ground selection line (First ground selection line: Kanamori, Figure 13),
a second ground selection line (Second ground selection line: Kanamori, Figure 13), and
a third ground selection line that are vertically stacked on the substrate (Third ground selection line: Kanamori, Figure 13),
wherein the first ground selection transistor, the second ground selection transistor, and the third ground selection transistor of each of the plurality of cell strings provide
a plurality of first ground selection transistors, a plurality of second ground selection transistors, and a plurality of third ground selection transistors (Each memory line including at least a first, second, and third ground selection transistor: Kanamori, Figure 13),
each of the first ground selection line, the second ground selection line, and the third ground selection line are commonly connected to at least one of the plurality of first ground selection transistors, at least one of the plurality of second ground selection transistors, and at least one of the plurality of third ground selection transistors (Each of the first, second, and third ground select transistors controlled in common with the respective ground selection transistors on other lines by a common ground selection line: Kanamori, Figure 13).
Regarding Claim 15, Kanamori discloses the semiconductor device of claim 11, further comprising:
a first separation structure and a second separation structure on the substrate and extending in a first direction (At least two separation structures extending in the first direction: Kanamori, col.12:6-10 and Kanamori, Figure 9);
a first ground selection line, a second ground selection line, and a third ground selection line that are vertically stacked on the substrate and between the first separation structure and the second separation structure (A separation structure located above the GSL structure: Kanamori, col.12:10-17; Ground selection lines are further necessarily electrically separated from the base substrate); and
a plurality of string selection lines horizontally spaced apart from each other (The string selection lines 1-6 being spaced at regular intervals: Kanamori, Figure 13) between the first separation structure and the second separation structure (The string selection lines being separated from the the memory cells and bit line by insulating structures: Kanamori, Figure 13),
wherein each of the first ground selection line, the second ground selection line, and the third ground selection line is a single conductive pattern extending in the first direction, and the first direction is parallel to the upper surface of the substrate (The first, second, and third ground selection lines extending in the first direction and parallel to the base substrate: Kanamori, Figure 13).
Regarding Claim 16, Kanamori discloses the semiconductor device of claim 15, further comprising:
a plurality of word lines that are vertically stacked between the third ground selection line and the plurality of string selection lines (A plurality of word lines vertically stacked between the ground selection lines and the string selection lines: Kanamori, Figure 13),
wherein each of the plurality of word lines is commonly connected to the memory cells positioned at a same level in the plurality of cell strings (Each memory cell at the same relative position in each memory string connected to a common word line: Kanamori, Figure 13).
Regarding Claim 17, Kanamori discloses the semiconductor device of claim 11, wherein
each of the plurality of cell strings further includes a common ground selection transistor connected in series to each other between the substrate and the first ground selection transistor (Kanamori only requires at least one of the ground select transistors have a first threshold voltage, the remaining transistors may all have the second threshold voltage. If the four ground select transistors are chosen from between GSL1b-GSL1f, all GSL1a transistors may considered part of the ‘remaining transistors,’ each programmed to the same voltage Vth2: Kanamori, Figure 13 and col.1:50-54).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,971,238 B2 to Kanamori, et al. (hereafter Kanamori) in view of US 9,412,462 B2 to Byung-Gook Park, et al. (hereafter Park) and further in view of US 10,276,250 B1 to Wei-Chen Chen, et al. (hereafter Chen).
Regarding Claim 18, Kanamori discloses the semiconductor device of claim 17, wherein
each of the plurality of cell strings further includes transistors connected in series to each other between the common ground selection transistor and the first ground selection transistor (A dummy transistor is the same as a standard memory cell, except it is used to store data nor typically addressable for the purposes of data storage. Taking the configuration of Kanamori, Figure 13, the first transistor GST1 may be considered the common ground transistor, GST2 has all characteristics of a dummy transistor, and the remaining ground select transistors the equivalent of the claim ground select transistors: Kanamori, Figure 13).
Although Kanamori discloses a common ground select transistor, a dummy transistor, and four individualized ground select transistors, wherein the dummy transistor is located between the common ground transistor and the specialized ground select transistors, it only discloses a single dummy transistor in this configuration. Implementing similar configurations with more than one dummy transistor was previously known in the art, however (See, for instance, Disclosing three dummy transistors located between the common ground select and the memory cells: Chen, Figure 3). Chen teaches the introduction of dummy memory cells are necessary because the common ground select transistor creates a functional edge, leading to disturbance on nearest cells. Introducing multiple dummy cells in this gap helps reduce the disturbance experienced by the array as a whole (Chen, col.2:43-60). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the additional buffer created by having multiple dummy cells, as in Chen, with the multiple gate select transistors or Kanamori, with a reasonable expectation of success. Both inventions are well known in the field of ground select gate management in memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,595,346 B2 to Changyun Lee, et al.: Disclosing a memory cell array deposed on a first substrate and a peripheral circuit deposed on a second substrate bonded to the first substrate and connected by vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
Prosecution Insights