Prosecution Insights
Last updated: July 17, 2026
Application No. 18/679,869

SEMICONDUCTOR MODULE

Non-Final OA §102
Filed
May 31, 2024
Priority
Jul 13, 2023 — JP 2023-115291
Examiner
FERNANDES, ERROL V
Art Unit
Tech Center
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
691 granted / 811 resolved
+25.2% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
15 currently pending
Career history
825
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
84.9%
+44.9% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 811 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshihara et al. US 2008/0217760 A1. Regarding claim 1, Yoshihara discloses: A semiconductor module (Figs. 1-6) comprising: a heat radiation plate (1 metal base); a first insulating substrate (2 insulating circuit board) disposed on a first surface of the heat radiation plate and having a semiconductor chip provided thereon; a frame-shaped case (5 outer resin case) surrounding the first insulating substrate; a plurality of external terminals (6 mounting external terminals) provided across an inside and an outside of the case and electrically connected to the semiconductor chip via a bonding wire (7 wire); and at least one second insulating substrate (10 terminal clamping frame) disposed between the heat radiation plate and the plurality of external terminals and having heat conductivity greater than that of the case, wherein the at least one second insulating substrate and the first surface of the heat radiation plate are bonded to each other by a heat conductive bonding material (11 adhesive). The examiner does not give patentable weight in regards to the claim limitation stating that “wherein each of the plurality of external terminals and the at least one second insulating substrate are joined to each other by press-fitting” since such a limitation is taken to be a product-by-process limitation and is considered nonlimiting. A product by process claim is directed to the product per se, no matter how actually made. See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al, 218 USPQ 289, 292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned" from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not. Regarding claim 12, Yoshihara discloses: The examiner does not give patentable weight in regards to the claim limitation stating that “wherein the case is formed by insert molding using each of the plurality of external terminals that is an insert part” since such a limitation is taken to be a product-by-process limitation and is considered nonlimiting. A product by process claim is directed to the product per se, no matter how actually made. See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al, 218 USPQ 289, 292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned" from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not. Allowable Subject Matter Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 2 stating “each of the plurality of second insulating substrates includes: an insulating plate; a first conductor disposed on a first surface of the insulating plate and bonded to the first surface of the heat radiation plate by the bonding material; and at least one second conductor disposed on a second surface of the insulating plate and separated for each of the plurality of external terminals”; of claim 4 stating “the second insulating substrate includes: an insulating plate, a first conductor disposed on a first surface of the insulating plate and bonded to the first surface of the heat radiation plate by the bonding material, and a plurality of second conductors arranged on a second surface of the insulating plate and separated for each of the plurality of external terminals”; and of claim 11 stating “wherein the bonding material is solder”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

May 31, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685220
MODULAR SYSTEMS IN PACKAGES, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS
3y 10m to grant Granted Jul 14, 2026
Patent 12677428
METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)
2y 10m to grant Granted Jul 07, 2026
Patent 12672530
ELECTRONIC PACKAGE
4y 2m to grant Granted Jun 30, 2026
Patent 12672575
SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jun 30, 2026
Patent 12672571
ELECTRONIC DEVICE
2y 6m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 811 resolved cases by this examiner. Grant probability derived from career allowance rate.

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