DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 6/23/2026 is acknowledged. The traversal is on the ground(s) that examination of all the claims can be made without serious burden. This is not found persuasive because as noted in the previous office action, the different embodiments contain mutually exclusive features such that prior art reading on one invention would not read on the other. Therefore a serious burden exists insofar as different fields of search and strategies/queries are required.
The requirement is still deemed proper and is therefore made FINAL.
Claim 16 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/23/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao et al. (US PG Pub 2025/0112166, hereinafter Tsao).
Regarding claim 9, figure 2 of Tsao discloses a semiconductor package comprising:
a wiring board (110);
a semiconductor chip (10) on a top surface of the wiring board and electrically connected to the wiring board;
a molding layer (UF1) between the wiring board and the semiconductor chip and molding the wiring board and the semiconductor chip; and
solder resist patterns (parts of 120) surrounded by the molding layer under the semiconductor chip, wherein the solder resist patterns are arranged under one side of the semiconductor chip.
Regarding claim 10, figure 2 of Tsao discloses a plurality of signal bumps (BP1) surrounded by the molding layer (UF1) between the wiring board (110) and the semiconductor chip (10), the plurality of signal bumps electrically connecting the wiring board and the semiconductor chip.
Regarding claim 11, figure 2 of Tsao discloses the plurality of signal bumps (BP1) are arranged in a line under a center of the semiconductor chip (10) along a first horizontal direction.
Regarding claim 12, figure 2 of Tsao discloses the solder resist patterns are arranged in a line along the first horizontal direction under a first edge of the semiconductor chip (10) extending in the first horizontal direction.
Regarding claim 13, figure 2 of Tsao discloses the solder resist patterns are arranged on one side of the plurality of signal bumps and are not arranged on an other side.
Note: A subset of the patterns can be interpreted to read on the claimed solder resist patterns such that the limitations are met.
Regarding claim 14, figure 2 of Tsao discloses the molding layer (UF1) comprises one or more voids (locations taken up by the bumps can be considered as voids within the molding layer) arranged between the plurality of signal bumps (BP1) and the solder resist patterns.
Regarding claim 15, figure 2 of Tsao discloses the solder resist patterns do not overlap the plurality of signal bumps (BP1) in a vertical direction.
Taso does not explicitly disclose the signal bumps includes a plurality of dummy bumps that are not electrically connected to the wiring board.
However, dummy bumps are well known in the art and it would have been obvious to include some dummy dumps to provide a greater mounting surface for the semiconductor chip to improve stability.
Allowable Subject Matter
Claims 1-8 and 17-20 are allowed.
Regarding claim 1, the closest prior art of record, Tsao et al. (US PG Pub 2025/0112166), either singularly or in combination, does not disclose or suggest the combination of limitations including “a semiconductor package comprising:
a wiring board including a wiring pattern;
a solder resist layer on a top surface of the wiring board, the solder resist layer defining an opening that exposes the wiring pattern;
solder resist patterns arranged in the opening; and
a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board, wherein the solder resist patterns are arranged under a first edge of one side of the semiconductor chip”.
Regarding claim 17, the closest prior art of record, Tsao et al. (US PG Pub 2025/0112166), either singularly or in combination, does not disclose or suggest the combination of limitations including “a semiconductor package comprising:
a wiring board including a wiring pattern;
a solder resist layer on a top surface of the wiring board, the solder resist layer defining an opening that exposes the wiring pattern;
a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board;
a molding layer in the opening between the wiring board and the semiconductor chip and molding the wiring board and the semiconductor chip;
solder resist patterns arranged in the opening between the wiring board and the semiconductor chip and surrounded by the molding layer; and
plurality of signal bumps surrounded by the molding layer between the wiring board and the semiconductor chip, the plurality of signal bumps electrically connecting the wiring board and the semiconductor chip, wherein the plurality of signal bumps are arranged in a line under a center of the semiconductor chip along a first horizontal direction, and
wherein the solder resist patterns are arranged in a line along the first horizontal direction under a first edge of the semiconductor chip extending in the first horizontal direction”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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