DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 27, 2026, has been entered.
Claims 1-18 are pending in this office action and presented for examination. Claims 1-2, 4, 6-7, 10-13, 16, and 18 are newly amended by the response received April 27, 2026.
Specification
In the amendment to the specification received April 27, 2026, line 7 of paragraph [0054], the word “structure” has been amended to be “rules” without any markup (e.g., strikethrough of “structure” and underlining of “rules”). Therefore, it is unclear as to whether “structure” or “rules” is intended to be disclosed in the context in which it resides. While the examiner has nevertheless sent out an office action rather than a notice of non-compliant amendment for the purposes of compact prosecution, Examiner recommends resubmitting the amendment to paragraph [0054] with the further markup noted above to ensure that a patent that issues from the instant application includes the aforementioned “rules” language.
Drawings
The drawings are objected to because:
In FIG. 9 as amended on April 27, 2026, step 908, “evected” should be “evicted”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 12 and 18 are objected to because of the following informalities. Appropriate correction is required.
In claim 12, line 3, “updating status” should be “updating a status” for grammatical clarity. (Also see, for example, claim 6, lines 1-2.)
In claim 18, line 3, “updating status” should be “updating a status” for grammatical clarity. (Also see, for example, claim 6, lines 1-2.)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a mutual write-after-write data dependency” in lines 15-16. However, it is indefinite as to whether this mutual write-after-write data dependency is the same as, or different from, “a mutual write-after-write data dependency” as recited in claim 1, line 14.
Claim 1 recites the limitation “the mutual write-after-write data dependency” in line 19. However, it is indefinite as to whether the antecedent basis for this limitation is “a mutual write-after-write data dependency” as recited in claim 1, line 14, or “a mutual write-after-write data dependency” as recited in claim 1, lines 15-16.
Claims 2-6 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 4 recites the limitation “the deallocating” in line 1. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 1, line 16, or “deallocating” in claim 1, line 19.
Claim 4 recites the limitation “The method of Claim 1, wherein the deallocating comprises deallocating the second set of physical registers by reference to the third mapper structure only based on the multiple instructions not having a mutual write-after-write data dependency” in lines 1-3. Claim 1, upon which claim 4 is dependent, recites the limitation “based on a group complete event for the instruction group, the mapper circuit determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure” in lines 13-21. However, the metes and bounds of the limitation of claim 4 are indefinite. For example, it is indefinite as to whether the “only” language is intended to further limit “the third mapper structure” or “based on”. For example, in the former case, it is unclear as to if, and how, claim 4 is further limiting the subject matter of claim 1, given that claim 1 recites, for example, “the third mapper structure rather than the second mapper structure” (and newly recites limitations corresponding to “based on the multiple instructions not having a mutual write-after-write data dependency). For example, in the latter case, it is unclear as to how the deallocating can be based only on the multiple instructions not having a mutual write-after-write data dependency, given that claim 1 appears to convey that the deallocating is also based on a group complete event for the instruction group.
Claim 5 recites the limitation “the deallocating” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 1, line 16, or “deallocating” in claim 1, line 19.
Claim 6 recites the limitation “the deallocating” in line 1. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 1, line 16, or “deallocating” in claim 1, line 19.
Claim 6 recites the limitation “The method of Claim 1, wherein the deallocating includes updating a status of deallocated physical registers in the second set of physical registers” in lines 1-2. Claim 1, upon which claim 6 is dependent, recites the limitation “deallocating the second set of physical registers” in claim 1, line 16, and claim 1, lines 19-20. However, the metes and bounds of claim 6 are indefinite. For example, it is unclear as to whether “deallocated physical registers” is the same as, or a proper subset of, “the second set of physical registers”. On one hand, the language of the limitation appears to imply the latter case, (“deallocated physical registers” “in the” “second set of physical registers”); on the other hand, claim 1 appears to imply the former case via conveying that the [entire] second set of physical registers is deallocated. For example, it is unclear as to how a step of deallocating a second set of physical registers can include updating a status of [already] deallocated physical registers in the second set of physical registers; in other words, it is unclear as to how physical registers can already be deallocated before the step of deallocating those physical registers is finished.
Claim 7 recites the limitation “the multiple instructions” in line 6. However, there is insufficient or unclear antecedent basis for this limitation in the claims. Note that this limitation is also recited in claim 7, line 10; claim 7, line 12; claim 7, line 17; claim 7, line 21; claim 7, line 22; claim 7, line 24; claim 7, line 25; claim 7, line 27; claim 10, line 3; and claim 10, line 4.
Claim 7 recites the limitation “a mutual write-after-write data dependency” in lines 22-23. However, it is indefinite as to whether this mutual write-after-write data dependency is the same as, or different from, “a mutual write-after-write data dependency” as recited in claim 7, line 21.
Claim 7 recites the limitation “the mutual write-after-write data dependency” in line 26. However, it is indefinite as to whether the antecedent basis for this limitation is “a mutual write-after-write data dependency” as recited in claim 7 line 21, or “a mutual write-after-write data dependency” as recited in claim 7, lines 22-23.
Claims 8-12 are rejected for failing to alleviate the rejections of claim 7 above.
Claim 10 recites the limitation “The processor of Claim 7, wherein the physical mapper circuit is configured to deallocate the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure only based on the multiple instructions not having a mutual write-after-write data dependency” in lines 1-4. Claim 7, upon which claim 10 is dependent, recites the limitation “based on a group complete event for the instruction group, determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure” in lines 20-28. However, the metes and bounds of the limitation of claim 10 are indefinite. For example, it is indefinite as to whether the “only” language is intended to further limit “the third mapper structure” or “based on”. For example, in the former case, it is unclear as to if, and how, claim 10 is further limiting the subject matter of claim 7, given that claim 7 recites, for example, “the third mapper structure rather than the second mapper structure” (and newly recites limitations corresponding to “based on the multiple instructions not having a mutual write-after-write data dependency). For example, in the latter case, it is unclear as to how the deallocating can be based only on the multiple instructions not having a mutual write-after-write data dependency, given that claim 7 appears to convey that the deallocating is also based on a group complete event for the instruction group.
Claim 11 recites the limitation “the deallocating” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 7, line 23, or “deallocating” in claim 7, line 26.
Claim 12 recites the limitation “the deallocating” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 7, line 23, or “deallocating” in claim 7, line 26.
Claim 13 recites the limitation “a mutual write-after-write data dependency” in lines 24-25. However, it is indefinite as to whether this mutual write-after-write data dependency is the same as, or different from, “a mutual write-after-write data dependency” as recited in claim 13, line 23.
Claim 13 recites the limitation “the mutual write-after-write data dependency” in line 28. However, it is indefinite as to whether the antecedent basis for this limitation is “a mutual write-after-write data dependency” as recited in claim 13, line 23, or “a mutual write-after-write data dependency” as recited in claim 13, lines 24-25.
Claim 13 recites the limitation “the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions” in lines 25-26. However, there is insufficient antecedent basis for this limitation in the claims. Note that this limitation is also recited in claim 13, lines 28-29.
Claims 14-18 are rejected for failing to alleviate the rejections of claim 13 above.
Claim 16 recites the limitation “The design structure of Claim 13, wherein the mapper circuit is configured to deallocate the second set of physical registers previously allocated to the logical registers targeted by the instructions by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency” in lines 1-4. Claim 13, upon which claim 16 is dependent, recites the limitation “based on a complete event for the instruction group, determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure” in lines 22-30. However, the metes and bounds of the limitation of claim 16 are indefinite. For example, it is indefinite as to whether the “only” language is intended to further limit “the third mapper structure” or “based on”. For example, in the former case, it is unclear as to if, and how, claim 16 is further limiting the subject matter of claim 13, given that claim 13 recites, for example, “the third mapper structure rather than the second mapper structure” (and newly recites limitations corresponding to “based on the multiple instructions not having a mutual write-after-write data dependency). For example, in the latter case, it is unclear as to how the deallocating can be based only on the multiple instructions not having a mutual write-after-write data dependency, given that claim 13 appears to convey that the deallocating is also based on a group complete event for the instruction group.
Claim 16 recites the limitation “The design structure of Claim 13, wherein the mapper circuit is configured to deallocate the second set of physical registers previously allocated to the logical registers targeted by the instructions by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency” in lines 1-4. Claim 13, upon which claim 16 is dependent, recites the limitation “based on a complete event for the instruction group, determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure” in lines 22-30. Therefore, it is indefinite as to whether the “instructions” of claim 16 are the same as, or different from, the “multiple instructions” of claim 13.
Claim 17 recites the limitation “the deallocating” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 13, line 25, or “deallocating” in claim 13, line 28.
Claim 18 recites the limitation “the deallocating” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “deallocating” in claim 13, line 25, or “deallocating” in claim 13, line 28.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 7-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. Note that while claim 7 recites a processor comprising a cache memory and a processor core, the processor core including physical registers and a mapper circuit, claim 13 (as well as the specification) explicitly discloses the possibility of the aforementioned elements being included within a design structure that is embodied in a machine-readable storage device. Examiner also notes that in the context of the instant invention, “physical” is not necessarily synonymous with “hardware”. (For example, claim 13 recites a design structure, embodied in a machine-readable storage device, comprising physical registers. For example, the instant application at least in part uses “physical” to describe particular registers to distinguish such particular registers from “logical” registers, in the context of register renaming.) Examiner recommends reciting a “hardware mapper circuit” rather than a “physical mapper circuit”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno et al. (Bonanno) (US 20200159535 A1).
Consider claim 1, Bonanno discloses a method of data processing ([0061], lines 3-4, data processing) in a data processing system ([0028], lines 1-3, computer system 10 is shown in the form of a computing device, also referred to as a processing device) including a processor ([0024], line 4, processor), the method comprising: a mapper circuit ([0036], line 6, instruction sequencing unit 104), based on receiving an instruction group of multiple instructions ([0054], lines 5-6, group of instructions) for dispatch ([0036], lines 5-6, instruction dispatch unit 102), establishing, in a first mapper structure, mappings of logical registers targeted by the multiple instructions to a first set of physical registers in the processor ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers); the mapper circuit maintaining, in a second mapper structure, prior mappings for the logical registers ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); the mapper circuit recording, in a third mapper structure, a second set of physical registers previously allocated to the logical registers targeted by the multiple instructions ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number); based on a flush event for the instruction group, the mapper circuit restoring the prior mappings from the second mapper structure to the first mapper structure ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); and based on a group complete event for the instruction group, the mapper circuit determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure (Examiner notes that this limitation is a contingent limitation. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Examiner recommends amending the limitations to remove the contingent aspect of the limitations).
Bonanno does not explicitly disclose that the third mapper structure has a lower access latency than the second mapper structure. To any extent to which such is not implicitly or inherently disclosed via the disclosure of the IBM Z/Architecture disclosed in paragraph [0025], lines 4-5, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the third mapper structure to have an access latency that is lower than a particular access latency of the second mapper structure in order to increase system performance relative to the third mapper structure having an access latency that is higher than that particular access latency of the second mapper structure. Alternatively, this modification merely entails simple substitution of one known element (a third mapper structure) for another (the same third mapper structure, but with a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure) to obtain predictable results (the invention of Bonanno, wherein the third mapper structure of Bonanno has a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, Bonanno discloses the method of Claim 1, wherein recording the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions includes recording, with a completion structure, the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
Consider claim 3, Bonanno discloses the method of Claim 1 (see above), wherein the first mapper structure is a working set mapper ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers) and the second mapper structure is a partitioned mapper history buffer ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush; [0040], lines 2-5, The MHB 114 may be logically an in-order list of evicted mappings from the MWS 110 of FIG. 2. The MHB 114 can be structured in various ways, such as being partitioned by logical register number).
Consider claim 4, Bonanno discloses the method of Claim 1 (see above), wherein the deallocating comprises deallocating the second set of physical registers by reference to the third mapper structure only based on the multiple instructions not having a mutual write-after-write data dependency ([0046], lines 5-7, multiple writers within a group to the same logical register; note that when multiple instructions write to a same logical register, a first instruction writing after a second instruction results in the second instruction not writing after the first instruction, and vice versa; and a first instruction writing after a second instruction does not cause the second instruction to be executed again to write after the first instruction executed again, and vice versa).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno as applied to claim 1 above, and further in view of Burky et al. (Burky) (US 20040215938 A1).
Consider claim 5, Bonanno discloses the method of Claim 1 (see above), wherein: the third mapper structure is a completion structure ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information). However, Bonanno does not explicitly disclose the deallocating includes indexing into the completion structure utilizing an instruction group identifier assigned to the instruction group.
On the other hand, Burky discloses indexing into a completion structure utilizing an instruction group identifier assigned to an instruction group ([0036], lines 4-6, the instruction group identifiers (Gtags) from the sources are sent to the group completion table (GCT); FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burky with the invention of Bonanno in order to facilitate the use of the GCT in Bonanno, given that a table must be indexed in order to be used. Alternatively, this modification merely entails combining prior art elements (the GCT of Bonanno, and an instruction group identifier that indexes a GCT of Burky) according to known methods (the teaching of Burky reflects the use of instruction group identifiers to index a GCT being known) to yield predictable results (the invention of Bonanno, wherein the GCT of Bonanno is indexed using an instruction group identifier), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno as applied to claim 1 above, and further in view of AAPA.
Consider claim 6, Bonanno discloses the method of Claim 1 (see above), but does not explicitly disclose that the deallocating includes updating a status of physical registers in a free list structure. To any extent to which such is not implicitly or inherently taught by Bonnano via Bonanno’s teachings of physical register allocation and deallocation throughout the specification (e.g., Bonnano, [0037], lines 2-3), AAPA explicitly discloses deallocating includes updating status of the physical registers in a free list structure (FIG. 8, labelled PRIOR ART, deallocate RTAGs 822, Free list 820). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of AAPA with the invention of Bonanno in order to facilitate the physical register allocation and deallocation of Bonnano, given that the status of a physical register as allocatable or not allocatable must be known in order to perform the physical register allocation and deallocation. Alternatively, this modification merely entails combining prior art elements (the physical register deallocating of Bonanno, and the free list of AAPA) according to known methods (the teaching of AAPA reflects the use of a free list in the context of physical register deallocating is known) to yield predictable results (the invention of Bonanno, entailing a free list to facilitate the physical register deallocating), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Response to Arguments
Applicant on page 9 argues: “The Examiner indicates that certain claims may be newly considered indefinite. Without conceding the correctness of the rejections, and merely to advance prosecution, Applicant amends the claims as presented herein and respectfully submits that the claims are not indefinite under § 112(b).”
In view of the aforementioned amendments, various potential indefinite issues indicated in the advisory action are precluded.
Applicant on page 9 argues: ‘The Examiner seems to maintain the rejection of claims 7-12 under 35 U.S.C. § 101 because these claims can allegedly encompass a software per se embodiment. Applicant respectfully disagrees for at least the reason that claim 7 is amended to recite "a physical mapper circuit" which precludes interpreting the claim as software per se.’
However, Examiner notes that in the context of the instant invention, “physical” is not necessarily synonymous with “hardware”. (For example, claim 13 recites a design structure, embodied in a machine-readable storage device, comprising physical registers. For example, the instant application at least in part uses “physical” to describe particular registers to distinguish such particular registers from “logical” registers, in the context of register renaming.) Examiner recommends reciting a “hardware mapper circuit” rather than a “physical mapper circuit”.
Applicant across pages 9-10 argues: ‘The Examiner also seems to maintain the rejections of claims 1-18 under 35 U.S.C. § 103 as being obvious over various combinations of references. Regarding these rejections, Applicant submits that the art of record fails to disclose, teach, or suggest at least "based on a group complete event for the instruction group, the mapper circuit determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure" as recited in amended claim 1 and as similarly recited in amended claims 7 and 13. Support for this amendment can be found at least in FIG. 10 and the associated description.’
In view of the aforementioned amendments, the previously presented prior art rejections of claims 7 and 13 are withdrawn. However, the previously presented prior art rejection of claim 1 is maintained, in view of claim 1 being a method claim and the newly added limitation reproduced above being a contingent limitation. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Applicant on page 10 argues: “In view of the replacement sheets submitted herewith, Applicant requests the Examiner to withdraw the drawing objections.”
In view of the aforementioned replacement sheets, the previously presented objections to the drawings are withdrawn (and the potential issues noted in the advisory action are precluded). However, the aforementioned replacement sheets appear to catalyze a further objectionable issue — see the drawings section above.
Applicant on page 11 argues: “The examiner has objected to Applicant's previous amendments to the specification as allegedly adding new matter. Without conceding the correctness of the objections, and merely to advance prosecution, Applicant amends paragraph [0054] of the application as presented herein. Applicant submits that the amendments merely correct a typographical error regarding the numbering of the design rules of the originally filed application and therefore do not constitute new matter. Applicant requests the Examiner to withdraw the specification objections.”
In view of the aforementioned amendments, the previously presented objection to the specification is withdrawn. However, in the amendment to the specification received April 27, 2026, line 7 of paragraph [0054], the word “structure” has been amended to be “rules” without any markup (e.g., strikethrough of “structure” and underlining of “rules”). Therefore, it is unclear as to whether “structure” or “rules” is intended to be disclosed in the context in which it resides. While the examiner has nevertheless sent out an office action rather than a notice of non-compliant amendment for the purposes of compact prosecution, Examiner recommends resubmitting the amendment to paragraph [0054] with the further markup noted above to ensure that a patent that issues from the instant application includes the aforementioned “rules” language.
Applicant across pages 11-12 argues the indefinite rejection of claims 2 and 4.
As conveyed in the Advisory Action, Examiner is withdrawing the aforementioned indefinite rejections of claims 2 and 4.
Applicant on page 12 argues: ‘With regards to claim 6, the claim is amended to read "wherein the deallocating includes updating a status of deallocated physical registers in the second set of physical registers in a free list structure." Alongside the amendments to claim 1, the claim now clearly refers back to the second set of physical registers. In light of the amendment, the claim is definite and the rejection should be withdrawn.’
However, the metes and bounds of the limitation remain indefinite, as it is unclear as to whether “deallocated physical registers” is the same as, or a proper subset of, “the second set of physical registers”. On one hand, the language of the limitation appears to imply the latter case, (“deallocated physical registers” “in the” “second set of physical registers”); on the other hand, claim 1 appears to imply the former case via conveying that the [entire] second set of physical registers is deallocated. For example, it is unclear as to how a step of deallocating a second set of physical registers can include updating a status of [already] deallocated physical registers in the second set of physical registers; in other words, it is unclear as to how physical registers can already be deallocated before the step of deallocating those physical registers is finished.
Applicant on page 12 argues: “With regards to claim 7, the claim is amended to address the rejection under 35 USC 112 by providing a consistent reference to the logical registers. In light of the amendments, the rejection should be withdrawn. The further rejection of claims 8-12 as depending on claim 7 and not alleviating the alleged antecedent basis error is moot.”
In view of the aforementioned amendment, the previously presented indefinite rejection regarding “the logical registers” language is withdrawn. However, a previously presented indefinite rejection regarding “the multiple instructions” appears to remain applicable — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 12 argues: “Claim 10-18 include amendments correcting the antecedent basis errors. In light of the amendments, Applicant respectfully requests that the rejections be withdrawn.”
In view of the aforementioned amendments, the associated previously presented rejections directed to antecedent basis errors for claims 10-18 are withdrawn.
Applicant on page 13 argues: “The examiner has explicitly acknowledged that claim 7 includes structural recitations of a processor, a cache memory and a processor core, physical registers and a mapper circuit. As the MPEP makes clear that software per se only applies when the alleged software is claimed as a product without any structural recitations, and claims 7-12 do include structural recitations, the claims are eligible under 35 USC 101.”
However, Examiner did not explicitly acknowledge that “claim 7 includes structural recitations”.
Applicant on page 13 argues: “Furthermore, claim 13 is an independent claim and the scope of claim 13 is entirely irrelevant to the interpretation of claims 7-12.”
However, Examiner submits that claim language in a second independent claim (which is part of the overall disclosure) may be relevant to claim interpretation of a first independent claim. For example, if a second independent claim conveys that a particular element can be implemented as software, Examiner submits it is reasonable for at least that reason for the broadest reasonable interpretation of that same particular element in a first independent claim to encompass a software implementation.
Applicant across pages 13-14 argues: ‘Regardless of whether Applicants specification and other claims indicate that the subject matter could be included in a design structure embodied in a machine-readable storage device, claimed embodiments are not required to, and typically do not, encompass every embodiment disclosed in the application. Claims 7-12 do not encompass an embodiment where the elements are included within a design structure that is embodied in a machine-readable storage device. They encompass embodiments where the elements are physical, tangible, elements (see, e.g., "a physical mapper circuit" recited in claim 7). In light of the express structural limitations of claim 7, the claim cannot be interpreted as software per se, and Applicant respectfully requests that the rejection of claims 7-12 be withdrawn.’
However, as conveyed in MPEP 2106.03, “A claim whose BRI covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter.” Examiner also notes that in the context of the instant invention, “physical” is not necessarily synonymous with “hardware”. (For example, claim 13 recites a design structure, embodied in a machine-readable storage device, comprising physical registers. For example, the instant application at least in part uses “physical” to describe particular registers to distinguish such particular registers from “logical” registers, in the context of register renaming.) Examiner recommends reciting a “hardware mapper circuit” rather than a “physical mapper circuit”.
Applicant across pages 15-16 argues: ‘Instead, the examiner alleges that it would have been obvious to modify the disclosure of Bonanno "for the third mapper structure to have an access latency that is lower than a particular access latency of the second mapper structure in order to increase system performance relative to the third mapper structure having an access latency that is higher than that particular latency of the second mapper structure. In the previously filed response, Applicant explicitly identified this defect by remarking that the examiner has merely asserted that such would have been common sense but has not provided any evidence establishing that this is true. Rather than responding to Applicant identifying this defect and providing such articulated reasoning, the examiner has simply reiterated that the allegedly obvious feature would be common sense. An examiner's assertion of "common sense" is not evidence. Nor, is such an assertion "articulated reasoning".’
Examiner submits that the provided rationale for obviousness reflects articulated reasoning with rational underpinning: one of ordinary skill in the art before the effective filing date of the claimed invention would understand a memory with lower access latency would take less time to access, and would understand that a memory that takes less time to access is desirable.
Applicant on page 16 argues: ‘Even setting aside the above failure to establish prima facie obviousness, the allegedly "common sense" obviousness would be to reduce latency and increase performance. But the allegedly obvious feature is not simply having a low latency. The particular feature at issue is "the third mapper structure having a lower access latency than the second mapper structure". The examiner has not even attempted to explain why it would be common sense to use a the third mapper structure with a lower access latency than the second mapper structure. Instead, the examiner has simply asserted that decreasing latency increases performance, and therefore the feature is obvious. The examiner's rejection is facially deficient, and does not provide a prima facie case of obviousness.’
However, as explained in the rejection, it would have been obvious to modify the disclosure of Bonanno for the third mapper structure to have an access latency that is lower than a particular access latency of the second mapper structure in order to increase system performance relative to the third mapper structure having an access latency that is higher than that particular latency of the second mapper structure. In other words, the rationale for obviousness took into account the third mapper structure having a lower access latency "than the second mapper structure".
Applicant on page 17 argues: ‘The examiner's submission is not a finding. The examiner cannot simply recite "the examiner submits" as a talismanic recitation and meet the requirements of establishing a prima facie case of obviousness. The examiner must make a finding supported by evidence and clearly articulated reasoning. The examiner has not even attempted to do so.’
However, it is unclear as to what aspects of the rejection Applicant is arguing necessitate evidence. For example, it is unclear as to whether Applicant is arguing that specific evidence must be provided that a memory can have a different access latency than another memory. For example, it is unclear as to whether Applicant is arguing that specific evidence must be provided that one memory of one access latency can be substituted for another memory of another access latency. Examiner generally submits that the evolution of memory technology across decades reflects newer memories having lower access latencies than—and replacing—older memories with higher access latencies.
Applicant across pages 17-18 argues: ‘Further, Applicant submits that the art of record fails to disclose, teach, or suggest at least "based on a group complete event for the instruction group, the mapper circuit determining whether the multiple instructions have a mutual write-after-write data dependency and, in response to determining that the multiple instructions do not have a mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure, and, in response to determining that the multiple instructions have the mutual write-after-write data dependency, deallocating the second set of physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the second mapper structure" as recited in amended claim 1 and as similarly recited in amended claims 7 and 13. Support for this amendment can be found at least in FIG. 10 and the associated description.’
In view of the aforementioned amendments, the previously presented prior art rejections of claims 7 and 13 are withdrawn. However, the previously presented prior art rejection of claim 1 is maintained, in view of claim 1 being a method claim and the newly added limitation reproduced above being a contingent limitation. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Examiner recommends amending the limitations to remove the contingent aspect of the limitations. Examiner also notes that claims 1, 7, and 13 are subject to various indefinite issues — see the Claim Rejections - 35 USC § 112 section above.
Conclusion
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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