DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-18 are pending in this office action and presented for examination. Claims 1-2, 6-7, 10-13, and 16-18 are newly amended by the response received December 15, 2025.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
Paragraph [0054], in the amended specification dated December 15, 2025, associates reference character 1270 with “test data files”; however, this association does not appear to be supported by the original disclosure and is therefore new matter. (Examiner further notes that the many other applications by the same assignee that also contain the subject matter of FIG. 12 do not appear to associate reference character 1270 with “test data files”.)
Paragraph [0054], in the amended specification dated December 15, 2025, discloses that the data structure types may further includes design structure 1290; however, this subject matter does not appear to be supported by the original disclosure and is therefore new matter. In addition, the associated deletion of design “rules” from the specification, to convey the aforementioned subject matter, is likewise new matter. (Examiner further notes that the many other applications by the same assignee that also contain the subject matter of FIG. 12 do not appear to convey the aforementioned subject matter.)
Drawings
The drawings are objected to because:
In FIG. 2 as amended on December 15, 2025, reference character 204 is directed to both “Instruction decode unit” and “Branch processing unit”.
In FIG. 5, element 502a is labeled “Buffer instance”, but element 502p is labeled “Buffer”.
FIG. 7 should be labeled as “PRIOR ART” in view of paragraph [0025], third-to-last line, of the original disclosure (paragraph [0039], third-to-last line, of the amended specification dated December 15, 2025).
In FIG. 8 as amended on December 15, 2025, the “PRIOR ART” label is removed, which is new matter.
In FIG. 8 as amended on December 15, 2025, element 822, “RTAGS” should be “RTAGs”.
In FIG. 8 as amended on December 15, 2025, element 824, “RTAGS” should be “RTAGs”.
In FIG. 9 as amended on December 15, 2025, step 908, “Update GCT with RTAGs” should be “Update GCT with evicted RTAGs”.
In FIG. 9 as amended on December 15, 2025, step 910, “Black” should be “Block”.
In FIG. 9 as amended on December 15, 2025, step 912, “instructon” should be “instruction”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, and 6-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “recording the physical registers previously allocated to the logical registers targeted by the multiple instructions includes recording, with a completion structure, the physical registers previously allocated to the logical registers targeted by the multiple instructions” in lines 1-4. However, it is indefinite as to how “recording the physical registers previously allocated to the logical registers targeted by the multiple instructions” can include both “recording, with a completion structure, the physical registers previously allocated to the logical registers targeted by the multiple instructions” as well as another distinct sub-step that is in addition to the aforementioned recording, which is a scenario encompassed by the claim language in view of the open-ended “includes” language.
Claim 4 recites the limitation “the deallocating comprises deallocating the physical registers by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency” in lines 1-3. However, it is indefinite as to how “the deallocating [the physical registers previously allocated to the logical registers targeted by the instructions by reference to the third mapper structure rather than the second mapper structure]” can include both “deallocating the physical registers by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency” as well as another distinct sub-step that is in addition to the aforementioned deallocating, which is a scenario encompassed by the claim language in view of the open-ended “comprises” language.
Claim 4 recites the limitation “the physical registers” in lines 1-2. However, it is indefinite as to whether the antecedent basis for this limitation is “physical registers” in claim 1, line 5, or “physical registers” in claim 1, line 8. For the purposes of this office action, Examiner is interpreting this limitation as “the physical registers previously allocated to the logical registers targeted by the multiple instructions”.
Claim 4 recites the limitation “the instructions” in line 2. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 6 recites the limitation “physical registers” in line 2. However, it is indefinite as to whether these physical registers are the same as, or different from, “the physical registers previously allocated to the logical registers targeted by the multiple instructions” as recited in claim 1, lines 13-15. Similarly, it is indefinite as to whether these physical registers are the same as, or different from, “physical registers” in claim 1, line 5. If the same in either case, antecedent basis language and consistent limitation language should be used for clarity.
Claim 7 recites the limitation “the multiple instructions” in line 6. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 7 recites the limitation “the multiple instructions” in lines 11-12. However, it is indefinite as to whether the antecedent basis for this limitation is “multiple instructions” in claim 7, line 6, or “multiple instructions” in claim 7, line 10. Note that this limitation is also recited in claim 7, line 16; claim 7, lines 20-21; and claim 10, lines 2-3.
Claim 7 recites the limitation “the logical registers” in lines 13-14. However, it is indefinite as to whether the antecedent basis for this limitation is “logical registers” in claim 7, line 6, or “logical registers” in claim 7, line 11.
Claim 7 recites the limitation “the logical registers targeted by the multiple instructions” in line 16. However, it is indefinite as to whether the antecedent basis for this limitation is the logical registers of the limitation “the multiple instructions target logical registers” in claim 7, line 6, or the logical registers of the limitation “logical registers targeted by the multiple instructions” in claim 7, lines 11-12. Note that this limitation is also recited in claim 7, lines 20-21, and claim 10, lines 2-3.
Claims 8-12 are rejected for failing to alleviate the rejections of claim 7 above.
Claim 10 recites the limitation “the instructions” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation in the claims is “instructions” in claim 7, line 4; “instructions” in claim 7, line 5; “multiple instructions” in claim 7, line 6, or “multiple instructions” in claim 7, line 10.
Claim 12 recites the limitation “the physical registers” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “physical registers” in claim 7, line 4; “physical registers” in claim 7, line 12; or “physical registers” in claim 7, line 15. For the purposes of this office action, Examiner is interpreting this limitation as “the physical registers previously allocated to the logical registers targeted by the multiple instructions”.
Claim 13 recites the limitation “logical registers targeted by the instructions” in lines 14-15. However, it is indefinite as to whether these logical registers are the same as, or different from, the logical registers of the limitation “the instructions target logical registers” in claim 13, line 9. If the same, antecedent basis language should be used for clarity.
Claim 13 recites the limitation “the logical registers targeted by the instructions” in lines 16-17. However, it is indefinite as to whether the antecedent basis for this limitation is the logical registers of the limitation “the instructions target logical registers” in claim 13, line 9, or the logical registers of the limitation “logical registers targeted by the instructions” in claim 13, lines 14-15. Note that this limitation is also recited in claim 13, line 19; claim 13, lines 23-24; and claim 16, lines 2-3.
Claims 14-18 are rejected for failing to alleviate the rejections of claim 13 above.
Claim 18 recites the limitation “the physical registers” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “physical registers” in claim 13, line 7; “physical registers” in claim 13, line 15; or “physical registers” in claim 13, line 18. For the purposes of this office action, Examiner is interpreting this limitation as “the physical registers previously allocated to the logical registers targeted by the multiple instructions”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 7-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. Note that while claim 7 recites a processor comprising a cache memory and a processor core, the processor core including physical registers and a mapper circuit, claim 13 (as well as the specification) explicitly discloses the possibility of the aforementioned elements being included within a design structure that is embodied in a machine-readable storage device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno et al. (Bonanno) (US 20200159535 A1).
Consider claim 1, Bonanno discloses a method of data processing ([0061], lines 3-4, data processing) in a data processing system ([0028], lines 1-3, computer system 10 is shown in the form of a computing device, also referred to as a processing device) including a processor ([0024], line 4, processor), the method comprising: a mapper circuit ([0036], line 6, instruction sequencing unit 104), based on receiving an instruction group of multiple instructions ([0054], lines 5-6, group of instructions) for dispatch ([0036], lines 5-6, instruction dispatch unit 102), establishing, in a first mapper structure, mappings of logical registers targeted by the multiple instructions to physical registers in the processor ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers); the mapper circuit maintaining, in a second mapper structure, prior mappings for the logical registers ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); the mapper circuit recording, in a third mapper structure, physical registers previously allocated to the logical registers targeted by the multiple instructions ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number); based on a flush event for the instruction group, the mapper circuit restoring the prior mappings from the second mapper structure to the first mapper structure ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); and based on a complete event for the instruction group, the mapper circuit deallocating the physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure ([0023], lines 34-38, the GCT can contain the remaining information for performing intermediate register deallocation upon group completion or upon a flush. Embodiments are applicable in systems with or without sub-registers; [0045], lines 12-14, upon group completion, any of the intermediate mappings that do not survive the group can be deallocated from the GCT 116; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
Bonanno does not explicitly disclose that the third mapper structure has a lower access latency than the second mapper structure. To any extent to which such is not implicitly or inherently disclosed via the disclosure of the IBM Z/Architecture disclosed in paragraph [0025], lines 4-5, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the third mapper structure to have an access latency that is lower than a particular access latency of the second mapper structure in order to increase system performance relative to the third mapper structure having an access latency that is higher than that particular access latency of the second mapper structure. Alternatively, this modification merely entails simple substitution of one known element (a third mapper structure) for another (the same third mapper structure, but with a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure) to obtain predictable results (the invention of Bonanno, wherein the third mapper structure of Bonanno has a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, Bonanno discloses the method of Claim 1, wherein recording the physical registers previously allocated to the logical registers targeted by the multiple instructions includes recording, with a completion structure, the physical registers previously allocated to the logical registers targeted by the multiple instructions ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
Consider claim 3, Bonanno discloses the method of Claim 1 (see above), wherein the first mapper structure is a working set mapper ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers) and the second mapper structure is a partitioned mapper history buffer ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush; [0040], lines 2-5, The MHB 114 may be logically an in-order list of evicted mappings from the MWS 110 of FIG. 2. The MHB 114 can be structured in various ways, such as being partitioned by logical register number).
Consider claim 4, Bonanno discloses the method of Claim 1 (see above), wherein the deallocating comprises deallocating the physical registers by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency ([0046], lines 5-7, multiple writers within a group to the same logical register; note that when multiple instructions write to a same logical register, a first instruction writing after a second instruction results in the second instruction not writing after the first instruction, and vice versa; and a first instruction writing after a second instruction does not cause the second instruction to be executed again to write after the first instruction executed again, and vice versa).
Consider claim 7, Bonanno discloses a processor ([0028], lines 1-3, computer system 10 is shown in the form of a computing device, also referred to as a processing device) comprising: a cache memory ([0031], line 4, cache memory 32); and a processor core coupled to the cache memory ([0024], line 4, processor), the processor core including: physical registers for buffering operands of instructions ([0038], line 1, physical registers); at least one execution unit configured to execute instructions to produce operands ([0036], line 7, execution unit 106), wherein the multiple instructions target logical registers ([0002], line 5, logical registers); and a mapper circuit ([0036], line 6, instruction sequencing unit 104) having first ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers), second ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush), and third mapper structures ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number), wherein the mapper circuit is configured to perform: based on receiving an instruction group of multiple instructions ([0054], lines 5-6, group of instructions) for dispatch ([0036], lines 5-6, instruction dispatch unit 102), establishing, in the first mapper structure, mappings of logical registers targeted by the multiple instructions to physical registers ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers); maintaining, in the second mapper structure, prior mappings for the logical registers ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); recording, in the third mapper structure, physical registers previously allocated to the logical registers targeted by the multiple instructions ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number); based on a flush event for the instruction group, restoring the prior mappings from the second mapper structure to the first mapper structure ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); and based on a complete event for the instruction group, deallocating the physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure rather than the second mapper structure ([0023], lines 34-38, the GCT can contain the remaining information for performing intermediate register deallocation upon group completion or upon a flush. Embodiments are applicable in systems with or without sub-registers; [0045], lines 12-14, upon group completion, any of the intermediate mappings that do not survive the group can be deallocated from the GCT 116; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
Bonanno does not explicitly disclose that the third mapper structure has a lower access latency than the second mapper structure. To any extent to which such is not implicitly or inherently disclosed via the disclosure of the IBM Z/Architecture disclosed in paragraph [0025], lines 4-5, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the third mapper structure to have an access latency that is lower than a particular access latency of the second mapper structure in order to increase system performance relative to the third mapper structure having an access latency that is higher than that particular access latency of the second mapper structure. Alternatively, this modification merely entails simple substitution of one known element (a third mapper structure) for another (the same third mapper structure, but with a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure) to obtain predictable results (the invention of Bonanno, wherein the third mapper structure of Bonanno has a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 8, Bonanno discloses the processor of Claim 7, wherein the third mapper structure is a completion structure ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
Consider claim 9, Bonanno discloses the processor of Claim 7 (see above), wherein the first mapper structure is a working set mapper ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers) and the second mapper structure is a partitioned mapper history buffer ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush; [0040], lines 2-5, The MHB 114 may be logically an in-order list of evicted mappings from the MWS 110 of FIG. 2. The MHB 114 can be structured in various ways, such as being partitioned by logical register number).
Consider claim 10, Bonanno discloses the processor of Claim 7 (see above), wherein the mapper circuit is configured to deallocate the physical registers previously allocated to the logical registers targeted by the multiple instructions by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency ([0046], lines 5-7, multiple writers within a group to the same logical register; note that when multiple instructions write to a same logical register, a first instruction writing after a second instruction results in the second instruction not writing after the first instruction, and vice versa; and a first instruction writing after a second instruction does not cause the second instruction to be executed again to write after the first instruction executed again, and vice versa).
Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno as applied to claims 1 and 7 above, and further in view of Burky et al. (Burky) (US 20040215938 A1).
Consider claim 5, Bonanno discloses the method of Claim 1 (see above), wherein: the third mapper structure is a completion structure ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information). However, Bonanno does not explicitly disclose the deallocating includes indexing into the completion structure utilizing an instruction group identifier assigned to the instruction group.
On the other hand, Burky discloses indexing into a completion structure utilizing an instruction group identifier assigned to an instruction group ([0036], lines 4-6, the instruction group identifiers (Gtags) from the sources are sent to the group completion table (GCT); FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burky with the invention of Bonanno in order to facilitate the use of the GCT in Bonanno, given that a table must be indexed in order to be used. Alternatively, this modification merely entails combining prior art elements (the GCT of Bonanno, and an instruction group identifier that indexes a GCT of Burky) according to known methods (the teaching of Burky reflects the use of instruction group identifiers to index a GCT being known) to yield predictable results (the invention of Bonanno, wherein the GCT of Bonanno is indexed using an instruction group identifier), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 11, Bonanno discloses the processor of Claim 7 (see above), wherein: the third mapper structure is a completion structure ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information). However, Bonanno does not explicitly disclose the deallocating includes the mapping circuit indexing into the completion structure utilizing an instruction group identifier assigned to the instruction group.
On the other hand, Burky discloses indexing into a completion structure utilizing an instruction group identifier assigned to an instruction group ([0036], lines 4-6, the instruction group identifiers (Gtags) from the sources are sent to the group completion table (GCT); FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burky with the invention of Bonanno in order to facilitate the use of the GCT in Bonanno, given that a table must be indexed in order to be used. Alternatively, this modification merely entails combining prior art elements (the GCT of Bonanno, and an instruction group identifier that indexes a GCT of Burky) according to known methods (the teaching of Burky reflects the use of instruction group identifiers to index a GCT being known) to yield predictable results (the invention of Bonanno, wherein the GCT of Bonanno is indexed using an instruction group identifier), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno as applied to claims 1 and 7 above, and further in view of AAPA.
Consider claim 6, Bonanno discloses the method of Claim 1 (see above), but does not explicitly disclose that the deallocating includes updating a status of physical registers in a free list structure. To any extent to which such is not implicitly or inherently taught by Bonnano via Bonanno’s teachings of physical register allocation and deallocation throughout the specification (e.g., Bonnano, [0037], lines 2-3), AAPA explicitly discloses deallocating includes updating status of the physical registers in a free list structure (FIG. 8, labelled PRIOR ART, deallocate RTAGs 822, Free list 820). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of AAPA with the invention of Bonanno in order to facilitate the physical register allocation and deallocation of Bonnano, given that the status of a physical register as allocatable or not allocatable must be known in order to perform the physical register allocation and deallocation. Alternatively, this modification merely entails combining prior art elements (the physical register deallocating of Bonanno, and the free list of AAPA) according to known methods (the teaching of AAPA reflects the use of a free list in the context of physical register deallocating is known) to yield predictable results (the invention of Bonanno, entailing a free list to facilitate the physical register deallocating), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 12, Bonanno discloses the processor of Claim 7 (see above), but does not explicitly disclose that the mapper circuit has a free list structure; and the deallocating includes the mapper circuit updating status of the physical registers in the free list structure. To any extent to which such is not implicitly or inherently taught by Bonnano via Bonanno’s teachings of physical register allocation and deallocation throughout the specification (e.g., Bonnano, [0037], lines 2-3), AAPA explicitly discloses a mapper circuit has a free list structure; and deallocating includes a mapper circuit updating status of physical registers in a free list structure (FIG. 8, labelled PRIOR ART, deallocate RTAGs 822, Free list 820). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of AAPA with the invention of Bonanno in order to facilitate the physical register allocation and deallocation of Bonnano, given that the status of a physical register as allocatable or not allocatable must be known in order to perform the physical register allocation and deallocation. Alternatively, this modification merely entails combining prior art elements (the physical register deallocating of Bonanno, and the free list of AAPA) according to known methods (the teaching of AAPA reflects the use of a free list in the context of physical register deallocating is known) to yield predictable results (the invention of Bonanno, entailing a free list to facilitate the physical register deallocating), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Claim(s) 13-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno et al. (Bonanno) (US 20200159535 A1) in view of Krishna et al. (Krishna) (US 20150268959 A1).
Consider claim 13, Bonanno discloses a processor ([0028], lines 1-3, computer system 10 is shown in the form of a computing device, also referred to as a processing device) including: a cache memory ([0031], line 4, cache memory 32); and a processor core coupled to the cache memory ([0024], line 4, processor), the processor core including: physical registers for buffering operands of instructions ([0038], line 1, physical registers); at least one execution unit configured to execute instructions to produce operands ([0036], line 7, execution unit 106), wherein the instructions target logical registers ([0002], line 5, logical registers); and a mapper circuit ([0036], line 6, instruction sequencing unit 104) having first ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers), second ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush), and third mapper structures ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number), wherein the mapper circuit is configured to perform: based on receiving an instruction group of multiple instructions ([0054], lines 5-6, group of instructions) for dispatch ([0036], lines 5-6, instruction dispatch unit 102), establishing, in the first mapper structure, mappings of logical registers targeted by the instructions to physical registers ([0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers); maintaining, in the second mapper structure, prior mappings for the logical registers targeted by the instructions ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); recording, in the third mapper structure, physical registers previously allocated to the logical registers targeted by the instructions ([0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number); based on a flush event for the instruction group, restoring the prior mappings from the second mapper structure to the first mapper structure ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush); and based on a complete event for the instruction group, deallocating the physical registers previously allocated to the logical registers targeted by the instructions by reference to the third mapper structure rather than the second mapper structure ([0023], lines 34-38, the GCT can contain the remaining information for performing intermediate register deallocation upon group completion or upon a flush. Embodiments are applicable in systems with or without sub-registers; [0045], lines 12-14, upon group completion, any of the intermediate mappings that do not survive the group can be deallocated from the GCT 116; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
However, Bonanno does not explicitly disclose that the third mapper structure has a lower access latency than the second mapper structure. To any extent to which such is not implicitly or inherently disclosed via the disclosure of the IBM Z/Architecture disclosed in paragraph [0025], lines 4-5, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the third mapper structure to have an access latency that is lower than a particular access latency of the second mapper structure in order to increase system performance relative to the third mapper structure having an access latency that is higher than that particular access latency of the second mapper structure. Alternatively, this modification merely entails simple substitution of one known element (a third mapper structure) for another (the same third mapper structure, but with a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure) to obtain predictable results (the invention of Bonanno, wherein the third mapper structure of Bonanno has a lower access latency, wherein the lower access latency is lower than an access latency of the second mapper structure), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
In addition, Bonanno does not explicitly disclose a design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising the aforementioned processor.
On the other hand, Krishna discloses a design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising a processor ([0048], lines 1-7, the foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Krishna with the invention of Bonanno in order to facilitate semiconductor fabrication. Alternatively, this modification merely entails a combination of prior art elements (the processor of Bonanno, and RTL, for example, as explicitly disclosed by Krishna) according to known methods (Examiner submits that RTL is well-known, as reflected by the teaching of Krishna) to yield predictable results (the processor of Bonanno, implemented via RTL), which is an exemplary rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 14, the overall combination entails the design structure of Claim 13, wherein the third mapper structure is a completion structure (Bonanno, [0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information; [0044], lines 15-18, information in the MHB 114 and GCT 116 used for register deallocation can include the thread, physical register type, and physical register number).
Consider claim 15, the overall combination entails the design structure of Claim 13 (see above), wherein the first mapper structure is a working set mapper (Bonanno, [0037], lines 3-5, a working set mapper (MWS) 110 that tracks a current state of mapping logical registers to physical registers) and the second mapper structure is a partitioned mapper history buffer ([0037], lines 7-8, MHB 114 can track mapping history to enable restoration of the MWS 110 on a flush; [0040], lines 2-5, The MHB 114 may be logically an in-order list of evicted mappings from the MWS 110 of FIG. 2. The MHB 114 can be structured in various ways, such as being partitioned by logical register number).
Consider claim 16, the overall combination entails the design structure of Claim 13 (see above), wherein the mapper circuit is configured to deallocate the physical registers previously allocated to the logical registers targeted by the instructions by reference to the third mapper structure only based on the instructions not having a mutual write-after-write data dependency (Bonanno, [0046], lines 5-7, multiple writers within a group to the same logical register; note that when multiple instructions write to a same logical register, a first instruction writing after a second instruction results in the second instruction not writing after the first instruction, and vice versa; and a first instruction writing after a second instruction does not cause the second instruction to be executed again to write after the first instruction executed again, and vice versa).
Consider claim 18, the combination thus far discloses the design structure of Claim 13 (see above), but does not explicitly disclose that the mapper circuit has a free list structure; and the deallocating includes the mapper circuit updating status of the physical registers in the free list structure. To any extent to which such is not implicitly or inherently taught by Bonnano via Bonanno’s teachings of physical register allocation and deallocation throughout the specification (e.g., Bonnano, [0037], lines 2-3), Krishna further explicitly discloses a mapper circuit has a free list structure; and deallocating includes a mapper circuit updating status of physical registers in a free list structure (FIG. 2, free list 223; [0020], lines 11-13, the PR written to by instruction A can therefore be freed, and returned to the free list of physical registers in the processor). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the further teaching of Krishna with the previously explained combination of Bonanno and Krishna in order to facilitate the physical register allocation and deallocation of Bonnano, given that the status of a physical register as allocatable or not allocatable must be known in order to perform the physical register allocation and deallocation. Alternatively, this modification merely entails combining prior art elements (the physical register deallocating of Bonanno, and the free list of Krishna) according to known methods (the teaching of Krishna reflects the use of a free list in the context of physical register deallocating is known) to yield predictable results (the invention of Bonanno, entailing a free list to facilitate the physical register deallocating), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonanno and Krishna as applied to claim 13 above, and further in view of Burky et al. (Burky) (US 20040215938 A1).
Consider claim 17, the combination thus far entails the processor of Claim 13 (see above), wherein: the third mapper structure is a completion structure (Bonanno, [0037], lines 8-10, GCT 116 can assist in completion tracking of groups of instructions and assist in the tracking of register allocation history information). However, the combination thus far does not explicitly disclose the deallocating includes the mapping circuit indexing into the completion structure utilizing an instruction group identifier assigned to the instruction group.
On the other hand, Burky discloses indexing into a completion structure utilizing an instruction group identifier assigned to an instruction group ([0036], lines 4-6, the instruction group identifiers (Gtags) from the sources are sent to the group completion table (GCT); FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Burky with the combination of Bonanno and Krishna in order to facilitate the use of the GCT in Bonanno, given that a table must be indexed in order to be used. Alternatively, this modification merely entails combining prior art elements (the GCT of Bonanno, and an instruction group identifier that indexes a GCT of Burky) according to known methods (the teaching of Burky reflects the use of instruction group identifiers to index a GCT being known) to yield predictable results (the combination of Bonanno and Krishna, wherein the GCT of Bonanno is indexed using an instruction group identifier), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Response to Arguments
Applicant on page 7 argues: “In view of the replacement sheets submitted herewith, Applicant requests the Examiner to withdraw the drawing objections.”
Various previously presented objections to the drawings are withdrawn in view of the amendments to the drawings. However, other previously presented objections to the drawings remain applicable, and in various cases the amendments to the drawings introduce additional objectionable issues — see the drawings section above.
Applicant on page 7 argues: “The specification was objected to due to minor informalities including paragraph numbering and claim component numbering. Paragraph numbering of the specification was amended in the submitted Substitute Specification to address the noted informalities. In addition, Paragraphs 39 and 54 are amended in the substitute specification to address the remaining numbering issues. Applicant requests the Examiner to withdraw the specification objections.”
Various previously presented objections to the specification are withdrawn in view of the amendments to the specification. However, other previously presented objections to the specification remain applicable, and in various cases the amendments to the specification introduce additional objectionable issues — see the specification section above.
Applicant on page 7 argues: “Claims 7-18 are objected to due to informalities. Applicant has amended claims 7-18 in the manner requested by the examiner. In light of the amendments, Applicant understands the objections to be moot and requests that the objections be withdrawn.”
In view of the aforementioned amendments, the previously presented objections to the claims are withdrawn.
Applicant on page 8 argues: ‘With regards to claim 1, Applicant has amended the recitation in line 9 to refer to "the logical registers targeted by the multiple instructions." Similar amendments are made at claims 2 and 4. In light of the amendments, the rejection is now moot and should be withdrawn.’
In view of the aforementioned amendment, most aspects of the aforementioned rejection are withdrawn. However, Examiner notes that claim 4 does not appear to have been amended.
Applicant on page 8 argues: ‘Respectfully, the "includes" language does not require that there be another distinct sub-step. Rather, it encompasses both embodiments where the claimed sub-step occurs by itself and embodiments where the claimed sub-step occurs in conjunction with one or more additional sub- steps. The fact that the examiner cannot conceive of such an alternate embodiment does not render the scope of the claim unclear. Indeed, it appears that the examiner fully understands the metes and bounds of the claim. Rather, the examiner has not conceived of what other embodiments may be included within those metes and bounds. The examiner's inability to conceptualize other embodiments within the metes and bounds of an open ended claim is not the same as the metes and bounds of the claim being indefinite. As such, claim 2 is not indefinite, and the rejection should be withdrawn. Similar remarks apply mutatis mutandis to the rejection of claim 4, the rejection of which is improper for the same reasons.’
However, while it may be the case that the "includes" language does not require that there be another distinct sub-step, the broadest reasonable interpretation of the “includes” language still covers the scenario in which there is another distinct sub-step, and Examiner submits that the metes and bounds of this scenario must be definite. (As an analogy, while a claim directed to a “computer-readable medium” is not necessarily directed to a transitory computer-readable medium, the broadest reasonable interpretation of “computer-readable medium” may still encompass a transitory computer-readable medium and therefore be non-statutory.) As Examiner cannot conceive of such a distinct sub-step given the content of the cited limitation (recording the physical registers previously allocated to the logical registers targeted by the multiple instructions includes recording, with a completion structure, the physical registers previously allocated to the logical registers targeted by the multiple instructions), the recitation of “includes” appears to be at odds with the surrounding subject matter, and therefore the metes and bounds of the limitation are indefinite. Examiner notes this rejection is not based on any given instance of “includes” necessarily being indefinite, but rather a particular instance of “includes” in the particular context of the particular cited limitation. Examiner recommends reciting the third mapper structure is a completion structure in a manner which does not use open-ended language in the particular context in which it is currently being used (e.g., see claims 8 and 14).
Applicant on page 9 argues: ‘With regards to claim 6, the claim is amended to define "the deallocating includes updating a status of the physical registers in a free list structure." As amended, claim 6 does not refer back to either previous physical register. Instead, the claim refers to a new set of "physical registers in a free list structure". For at least this reason, the rejection of claim 6 under 35 USC 112 is traversed.’
However, claim 1 recites “deallocating the physical registers” in lines 13-14, and it is unclear as to whether Applicant is arguing that deallocating of [first] physical registers includes updating a status of [other] physical registers in a free list structure. Examiner also notes that claim 12 recites “physical registers” in a similar context in a manner that continues to refer back to previously recited physical registers.
Applicant on page 9 argues: ‘With regards to claim 7, the examiner asserts that the limitation "the logical registers" in lines 13-14 is indefinite as to whether the antecedent basis for this limitation is "logical registers" in claim 7, line 6, or "logical registers" in claim 7, 11. Claim 7 is amended such that the logical registers referred to in line 6 (the multiple instructions target logical registers) and the logical registers referred to in line 11 (logical registers targeted by the multiple instructions) are the same set of logical registers, and the logical registers in lines 13-14 refer to both those in line 6 and those in line 11. In light of this amendment, the rejection is moot.’
However, claim 7 as currently amended does not appear to necessitate that the two sets of logical registers noted above are the same.
Applicant on page 9 argues: “With further regards to claim 7, Applicant has amended the claims to remove the redundant [mapper circuit configured to perform...the mapper circuit deallocating/restoring] language. In light of this amendment, the further rejections of claim 12 are moot and should be withdrawn.”
In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn.
Applicant on page 9 argues: “With regards to claim 10, the claim is amended to be consistent with the interpretation adopted by the examiner, and the rejection is therefore moot.”
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 9 argues: ‘With regards to claim 11, the claim is amended to correct the limitation "the mapper structure" to "the mapper circuit", and the rejection is therefore moot.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 9 argues: ‘With regards to claim 12, the claim is amended to define that the mapper circuit has a free list structure. In light of this amendment, the rejection is moot.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 9 argues: ‘With regards to claim 13, the claim is amended to clarify that each of the recitations of "the local registers" refers to "the local registers targeted by the instructions".’
However, the claim limitation “the logical registers targeted by the instructions” remains indefinite, as it is unclear as to which of multiple previously recited limitations is intended to provide antecedent basis for this claim limitation. Specifically, it is indefinite as to whether the antecedent basis for "the logical registers targeted by the instructions" is the logical registers of the limitation “the instructions target logical registers” in claim 13, line 9, or the logical registers of the limitation “logical registers targeted by the instructions” in claim 13, lines 14-15.
Applicant on page 9 argues: ‘Claim 13 is further amended to correct redundant references to the mapper circuit perform functions.’
In view of the aforementioned amendments, the associated previously presented rejections are withdrawn.
Applicant on page 9 argues: ‘With regards to claim 16, the claim is amended to be consistent with the interpretation adopted by the examiner, and the rejection is therefore moot.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 10 argues: ‘With regards to claims 17 and 18, the claims are amended to clarify the identified indefiniteness.’
With respect to the amendments to correct the limitation "the mapper structure" to "the mapper circuit", the associated previously presented indefinite rejection is withdrawn. However, the antecedent basis of “the physical registers” appears to remain unclear — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 10 argues: “In light of the amendments, as well as the above remarks, Applicant respectfully requests that the rejections under 35 USC112 be withdrawn.”
Various previously presented rejections of the claims under 35 U.S.C. §112(b) are withdrawn in view of the amendments to the claims. However, other previously presented rejections of the claims under 35 U.S.C. §112(b) remain applicable, and in various cases the amendments to the claims introduce additional issues under 35 U.S.C. §112(b) — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 10 argues: “The examiner has explicitly acknowledged that claim 7 includes structural recitations of a processor, a cache memory and a processor core, physical registers and a mapper circuit. As the MPEP makes clear that software per se only applies when the alleged software is claimed as a product without any structural recitations, and claims 7-12 do include structural recitations, the claims are eligible under 35 USC 101.”
However, Examiner did not explicitly acknowledge that “claim 7 includes structural recitations”.
Applicant on page 10 argues: ‘Furthermore, claim 13 is an independent claim and the scope of claim 13 is entirely irrelevant to the interpretation of claims 7-12.”
However, Examiner submits that claim language in a second independent claim (which is part of the overall disclosure) may be relevant to claim interpretation of a first independent claim. For example, if a second independent claim conveys that a particular element can be implemented as software, Examiner submits it is reasonable for at least that reason for the broadest reasonable interpretation of that same particular element in a first independent claim to encompass a software implementation.
Applicant across pages 10-11 argue: “Regardless of whether Applicants specification and other claims indicate that the subject matter could be included in a design structure embodied in a machine-readable storage device, claimed embodiments are not required to, and typically do not, encompass every embodiment disclosed in the application. Claims 7-12 do not encompass an embodiment where the elements are included within a design structure that is embodied in a machine-readable storage device. In light of the express structural limitations of claim 7, the claim cannot be interpreted as software per se, and the rejection is improper.’
However, as conveyed in MPEP 2106.03, “A claim whose BRI covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter.”
As also conveyed in MPEP 2106.03, “For example, the BRI of machine readable media can encompass non-statutory transitory forms of signal transmission, such as a propagating electrical or electromagnetic signal per se. See In re Nuijten, 500 F.3d 1346, 84 USPQ2d 1495 (Fed. Cir. 2007). When the BRI encompasses transitory forms of signal transmission, a rejection under 35 U.S.C. 101 as failing to claim statutory subject matter would be appropriate. Thus, a claim to a computer readable medium that can be a compact disc or a carrier wave covers a non-statutory embodiment and therefore should be rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. See, e.g., Mentor Graphics v. EVE-USA, Inc., 851 F.3d at 1294-95, 112 USPQ2d at 1134 (claims to a "machine-readable medium" were non-statutory, because their scope encompassed both statutory random-access memory and non-statutory carrier waves).”
Therefore, while Applicant may not intend for the relevant claim to encompass a software per se embodiment, such does not preclude the claim, under the broadest reasonable interpretation, from encompassing a software per se embodiment.
Applicant on page 12 argues: ‘With respect, the examiner has not established nor does the Bonanno reference establish that one of skill in the art at the time of invention would have known that using a third mapper structure having a lower access latency than that of the second mapper structure would increase system performance. No evidence or argument has been provided to that effect. Instead the examiner appears to simply assume that it is common knowledge that doing so would "increase system performance". However, the examiner cannot simply assume that one of skill in the art would have known of benefits of the invention, nor can the examiner rely only on applicant's disclosure that there are benefits of the invention to assert that one of skill in the art would have been aware of those benefits.’
However, MPEP 2143.01 conveys that ‘A "motivation to combine may be found explicitly or implicitly in market forces; design incentives; the ‘interrelated teachings of multiple patents’; ‘any need or problem known in the field of endeavor at the time of invention and addressed by the patent’; and the background knowledge, creativity, and common sense of the person of ordinary skill." Zup v. Nash Mfg., 896 F.3d 1365, 1371, 127 USPQ2d 1423, 1427 (Fed. Cir. 2018) (quoting Plantronics, Inc. v. Aliph, Inc., 724 F.3d 1343, 1354 [107 USPQ2d 1706] (Fed. Cir. 2013) (citing Perfect Web Techs., Inc. v. InfoUSA, Inc., 587 F.3d 1324, 1328 [92 USPQ2d 1849] (Fed. Cir. 2009) (quoting KSR, 550 U.S. at 418-21)).’
Examiner submits that a person of ordinary skill in the art before the effective filing date of the claimed invention, with their background knowledge, creativity, and common sense, would have found it obvious to lower the access latency of a memory in order to increase performance.
Applicant on page 12 argues: “The examiner's remarks lack any finding that the substituted components and their functions were known in the art. As the examiner has not established at least one element of a simple substitution rationale, as required by the MPEP, prima facie obviousness based on simple substitution has not been established.”
However, Examiner submits that a memory having a lower access latency relative to another memory was known in the art. Examiner submits that substituting the memory implementing the third mapper structure of Bonanno with a memory with an access latency that is lower than an access latency of the second mapper structure does not run afoul of the simple substitution rationale.
Applicant on page 13 argues: “An identical rationale is provided by the examiner to allege obviousness of the same feature in each of independent claims 7 and 13. This rationale is deficient for the same reasons.”
Examiner’s responses to arguments above with respect to claim 1 are likewise applicable to the arguments directed to the aforementioned further claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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