Prosecution Insights
Last updated: August 14, 2026
Application No. 18/680,085

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §102§112
Filed
May 31, 2024
Priority
Aug 09, 2023 — JP 2023-129927
Examiner
RAMIREZ, ALEXANDRE XAVIER
Art Unit
Tech Center
Assignee
MIRISE Technologies Corporation
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
35 granted / 37 resolved
+34.6% vs TC avg
Minimal -2% lift
Without
With
+-2.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
19 currently pending
Career history
59
Total Applications
across all art units

Statute-Specific Performance

§103
53.8%
+13.8% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 37 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/31/2024- is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election of claims 1-5 without traverse in the reply filed on 07/02/2026 is acknowledged. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description in relevant drawings: 8. The Examiner believes the white portion of element 6 in figures 6-9 and 11 are element 8. However, it is not clear this is the case as this portion is not labeled. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 1 is objected to because of the following informalities: Claim 1 recites the limitations, “the pattern structure within ”. The Examiner believes these limitations should recite, “the pattern structure is within” in order for the claim to be written in idiomatic English. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 1, Claim 1 recites the limitation, “a second main surface opposite to the first main surface”. The Examiner finds this limitation to be indefinite because the term, “opposite” alone does not indicate how a first main surface and a second main surface are disposed. That is, the first main surface and second main surface must be oppositely disposed relative to a third object such as a vertical line or a substrate. Because Applicant’s FIG. 2B shows a second main surface is opposite to a first main surface relative to a substrate, the Examiner interprets the limitation as, “a second main surface opposite to the first main surface relative to a substrate”. Regarding Claims 2-5, these claims depend on claim 1 and are rejected for the same reason. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ota et al US 20230207392 A1. Ota et al will be referenced to as Ota henceforth. Regarding Claim 1, Ota teaches: “A semiconductor device comprising: a semiconductor substrate (semiconductor substrate 101, [0056], FIG. 7) having a first main surface (first main surface 105, [0175], FIG. 7), a second main surface opposite to the first main surface (second main surface 106, [0056], FIG. 7), and a side surface extending between the first main surface and the second main surface (plurality of side surfaces 101a, [0077], FIG. 7), the side surface being a cleavage plane (cutting line 121, [0175], FIGs. 1, 3-4, and 7: The substrate is divided along the plurality of side surfaces.) and including a first side surface (annotated FIG. 7 #1) and a second side surface (annotated FIG. 7 #1) opposite to each other in a first direction parallel to the first main surface and the second main surface (annotated FIG. 7 #1: The X-direction.), and a third side surface (annotated FIG. 7 #1) and a fourth side surface (annotated FIG. 7 #1) opposite to each other in a second direction parallel to the first main surface and the second main surface and perpendicular to the first direction (annotated FIG. 7 #1: The Y-direction); and a pattern structure (protective films 103, [0041], FIG. 7) having a protruding shape and disposed on the first main surface of the semiconductor substrate (FIG. 7: 103 protrudes over 102. 103 is on 105), wherein the pattern structure within a first predetermined distance from the first side surface along the first direction ([0078], FIG. 7: 103 is spaced away from the first side surface along the X-direction by an interval. Let the first predetermined distance be twice the interval.) and the pattern structure within the first predetermined distance from the second side surface along the first direction ([0078], FIG. 7: 103 is spaced away from the second side surface along the X-direction by an interval. Let the first predetermined distance be twice the interval.) are symmetrical with respect to a line extending in the second direction ([0078], FIG. 7: These pattern structures are symmetric with respect to a line passing through the center of the device traveling in the Y-direction.), and the pattern structure within a second predetermined distance from the third side surface along the second direction ([0078], FIG. 7: 103 is spaced away from the third side surface along the Y-direction by an interval. Let the second predetermined distance be twice the interval.) and the pattern structure within the second predetermined distance from the fourth side surface along the second direction ([0078], FIG. 7: 103 is spaced away from the third side surface along the Y-direction by an interval. Let the second predetermined distance be twice the interval.) are symmetrical with respect to a line extending in the first direction (FIG. 7: These pattern structures are symmetric with respect to a line passing through the center of the device traveling in the X-direction.).” PNG media_image1.png 1012 1046 media_image1.png Greyscale Annotated FIG. 7 #1 Regarding Claim 2, Ota teaches: “The semiconductor device according to claim 1, wherein the first predetermined distance is twice a scribe line width that is measured from each of the first side surface and the second side surface to the pattern structure along the first direction ([0078], FIG. 7: A scribe line width is an interval. A first predetermined distance is twice the interval.), and the second predetermined distance is twice a scribe line width that is measured from each of the third side surface and the fourth side surface to the pattern structure along the second direction ([0078], FIG. 7: A scribe line width is an interval. A second predetermined distance is twice the interval.).” Regarding Claim 3, Ota teaches: “The semiconductor device according to claim 1, wherein the second main surface of the semiconductor substrate has a higher residual stress than the first main surface of the semiconductor substrate ([0067], [0071], FIGs. 3-7: A first blade and a second blade cut through 101 at 106 at a grinding mark at a cutting line (or scribe line). US 20240258173 A1 paragraph [0049] teaches that this process forms a compressive, residual stress field at the scribe line at a mounted surface 3. Because the scribe line is not made on the opposite side of the device of Ota, this stress is not present at the first main surface. Therefore, the second main surface has a higher residual stress than the first main surface.). ” Regarding Claim 4, Ota teaches: “The semiconductor device according to claim 1, wherein each of the pattern structure within the first predetermined distance from the first side surface along the first direction, the pattern structure within the first predetermined distance from the second side surface along the first direction, the pattern structure within the second predetermined distance from the third side surface along the second direction, and the pattern structure within the second predetermined distance from the fourth side surface along the second direction is a protective film ([0041]: 103 is a protective film.). ” Regarding Claim 5, Ota teaches: “The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide ([0039]: substrate 101 is silicon carbide.). ” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 31, 2024
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
92%
With Interview (-2.1%)
3y 4m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 37 resolved cases by this examiner. Grant probability derived from career allowance rate.

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