Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 in the reply filed on August 4, 2026 is acknowledged. Claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 31, 2026 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the specification contains the following typographically errors, on page 10 paragraph 42 “For example, the interconnect 500,” this is understood to be For example, the interconnect array 600, on page 10 paragraphs 43 “As illustrated in FIG. 5B,” this is understood to be As illustrated in FIG. 6B, and on page 11 paragraph 43 “the singulated interconnect 500,” this is understood to be the singulated interconnect 600.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “wherein each of the leads has a chamfer with a nearly equal height,” on page 1 lines 25-26. The term “nearly” is a relative term which renders the claim indefinite. The term “nearly” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purposes, this limitation will be interpreted as wherein each of the leads has a chamfer with an equal height.
Claim 8 recites the limitation “wherein the leads are wettable flanks, on page 1 line 28. This limitation renders claim 8 because is unclear how the leads are wettable flank. The examiner notes that wettable flanks are appear to refer to a structure formed on the leads. See paragraphs 25 and 49. For examination purposes, this limitation will be interpreted as wherein the leads have wettable flanks.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nadarajah et al. (US 7,002,239).
Regarding Claim 1:
Nadarajah discloses a substrate with an array of interconnects for IC (integrated circuit) packages comprising:
die pads (die attach pads, See fig. 2A, figs. 2B, 2C, ref. no. 210 and col. 4 lines 39-62) for receiving dies; and
leads (electrical contact leads and dummy contact leads, See figs. 2B, 2C, ref. nos. 208, 214, and col. 4 lines 39-62) arranged to circumscribe the die pads, wherein a subset of the leads (electrical contact leads around the perimeter of the die attach pads in a device area, See figs. 2B, 2C, ref. nos. 208, 210, and col. 4 lines 39-62) of that are proximal to a periphery of the substrate (flat metal substrate of a device array area, See fig. 2A, ref. no. 206 and col. 4 lines 39-62) are opposed by dummy leads (dummy contact leads, See figs. 2B, 2C, ref. no. 214, col. 4 lines 47-67 and col. 5 lines 1-14).
Regarding Claim 2:
Nadarajah discloses wherein the dummy leads are configured to be removed during singulation of interconnects in the array of interconnects (the dummy leads are located on a portion of the substrate that is to be removed during singulation, See fig. 5B, ref. no. 214 and col. 7 lines 25-35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kitnarong et al. (US 2017/0294367) in view of In’t Veld et al. (US 7,115,443).
Regarding Claim 1:
Kitnarong discloses a substrate with an array of interconnects for IC (integrated circuit) packages comprising:
die pads (center support structure, See fig. 6, ref. no. 42 and paragraph 47) for receiving dies; and
leads (pins, See fig 6, ref. no. 44 and paragraphs 47-48) arranged to circumscribe the die pads, wherein a subset of the leads (pins around the perimeter of the leadframes, See figs. 6, ref. nos. 40a, 40b, 44 and paragraphs 47-48) of that are proximal to a periphery of the substrate (metal structure the matrix of leadframes are formed in, See fig. 6, ref. nos. 40, 40a, 40b, and paragraphs 47-48).
Kitnarong does not disclose the subset of leads are opposed by dummy leads.
In’t Veld discloses the subset of leads are opposed by dummy leads (the copper carrier has a symmetrical design along the sawing lines such that perimeter leadframes have leads that are opposed by dummy leads, See figs. 1-2, ref. nos. 1, 2, 4, col. 3 lines 33-54 and col. 4 lines 42-66. The examiner notes that a die pad and the leads surround the die pad are being referred to as a leadframe. See fig. 1, ref. nos. 1, 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate with an array of interconnects for IC packages of Kitnarong to include the subset of leads are opposed by dummy leads as taught by In’t Veld in order to provide a better alignment of the dicing blade during sawing. (See In’t Veld col. 3 lines 32-38).
Regarding Claim 2:
The above stated combination of Kitnarong and In’t Veld discloses wherein the dummy leads are configured to be removed during singulation of interconnects in the array of interconnects (the dummy leads are located on a portion of the copper carrier that is to be removed during singulation, See In’t Veld fig. 1, ref. nos. 2, 4, and col. 7 lines 25-35. The examiner notes that the dummy leads to the right of the rightmost saw line will be removed during dicing.).
Regarding Claim 3:
The above stated combination of Kitnarong and In’t Veld discloses the above stated substrate with an array of interconnected for IC packages.
The above stated combination of Kitnarong and In’t Veld does not disclose wherein the leads in the subset leads are galvanically isolated from the dummy leads.
Kitnarong discloses electrically isolating neighboring pins (See fig. 10B, ref. no. 44 and paragraph 61).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate with an array of interconnects for IC packages of Kitnarong and In’t Veld to include electrically isolating pins of IC devices from neighboring dummy pins as taught by Kitnarong in order to eliminate issues with testing the IC devices caused by the dummy pins being connected to the pins of the IC device. (See Kitnarong paragraph 62.)
Regarding Claim 4:
The above stated combination of Kitnarong and In’t Veld discloses wherein the subset of the leads are spaced apart from the dummy leads by about 300 micrometers or more (bottom surfaces of neighboring pins are spaced apart by approximately 400 micrometers, See Kitnarong figs. 8A-8D, ref. nos. 44, 48, and paragraphs 56-57).
Regarding Claim 6:
The above stated combination of Kitnarong and In’t Veld discloses wherein leads of the subset of the leads have a thickness that varies from about 65 micrometers (the portions of the pins that contain the groove have a thickness of approximately 50-100 micrometers, See Kitnarong fig. 8A and paragraph 56. The examiner notes that the thickness of the portions of the pins that contain the groove is calculated by subtracting the groove depth of approximately 100-150 micrometers from the thickness of the portions of the pins that do not contain the groove, about 200 micrometers.) to about 191 micrometers (the portions of the pins that do not contain the groove have a thickness of about 200 micrometers, See Kitnarong fig. 8A and paragraph 56).
The examiner also notes that the thickness variation of the leads is a result effective variable because adjusting the thickness variation of the leads adjusts the amount of metal that must be cut through to separate the leadframes. The examiner next points out that the thickness variate of the leads is recognized by the prior art as a result-effective variable. (half-etching the leads in the saw lanes reduces the amount of copper which is to be sawn, See In’t Veld col. 4 lines 63-67 and col. 5 lines 1-4.) The examiner now notes that optimization of result effective variables through routine experimentation is an obviousness expedient and not a patentable distinction. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have thickness of the leads vary from about 200 micrometers to about 65 micrometer to reduce the amount of metal which is to be sawn.
Regarding Claim 7:
The above stated combination of Kitnarong and In’t Veld discloses wherein each of the leads has a chamfer with a nearly equal height (the depth of the groove cut into the pins is uniform, See Kitnarong fig. 6, ref. no. 46, figs. 8A-8C, ref. nos. 48 and paragraphs 56-57).
Regarding Claim 8:
The above stated combination of Kitnarong and In’t Veld discloses the above stated substrate with an array of interconnected for IC packages.
The above stated combination of Kitnarong and In’t Veld does not disclose wherein the leads are wettable flanks.
Kitnarong discloses wettable flanks formed on the pins (See figs. 9-11B and paragraphs 59-64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate with an array of interconnects for IC packages of Kitnarong and In’t Veld to include wettable flanks formed on the pins as taught by Kitnarong in order to provide an improved solder connection. (See Kitnarong paragraphs 45 and 65.)
Claim 5 is are rejected under 35 U.S.C. 103 as being unpatentable over Kitnarong et al. (US 2017/0294367) and In’t Veld et al. (US 7,115,443) in view of Bemmerl et al. (US 2019/0189542).
Regarding Claim 5:
The above stated combination of Kitnarong and In’t Veld discloses the above stated substrate with an array of interconnected for IC packages.
The above stated combination of Kitnarong and In’t Veld does not disclose wherein a portion of the leads extend from a metallic plate.
Bemmeral discloses wherein a portion of the leads extend from a metallic plate (lead section extending from a copper conductive carrier, See fig. 42, ref. nos. 102, 106, paragraphs 38, 102, and 176-177).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate with an array of interconnects for IC packages of Kitnarong and In’t Veld to include a portion of the leads extend from a metallic plate as taught by Bemmeral in order to provide better heat dissipation for the pins connected to copper conductive carrier.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
"Systematic approach in testing the viability of mechanical partial-cut singulation process towards tin-plateable sidewalls for wettable flank on automotive QFN technology," to Cabading et al. discloses a partial cut singulation process for forming wettable flanks on a quad flat no-leads package. See figures 1-2, introduction and methodology sections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
Prosecution Insights