DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 6/16/26.
Applicant’s election without traverse of Group B (device claims 11-20), species B4 (Fig. 26) in the reply filed on 8/13/26 is acknowledged. Claims 1-10 are withdrawn.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Regarding:
CHINA 202111496903.X 12/08/2021
CHINA 202111496915.2 12/08/2021
CHINA 202111496033.6 12/08/2021
CHINA 202111496879.X 12/08/2021
CHINA 202111496045.9 12/08/2021
CHINA 202111496912.9 12/08/2021
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/31/24 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 11 recites the limitation “a plastic encapsulation layer wrapping the plurality of memory chips and the substrate”.
The metes and bounds of the claimed limitation can not be determined for the following reasons: the term “plastic encapsulation layer” lacks proper antecedent basis, as the term has already been used in claim 11 (“A packaging structure of a multi-layer stacked high-bandwidth memory, comprising: a substrate, a plurality of memory chips, and a plastic encapsulation layer”).
It is thus unclear if this is a different plastic encapsulation layer than already claimed, or if it is the same.
Claims 12-20 depend from claim 11 and inherit its deficiencies.
Claim 20 recites the limitation “the plurality of second pads are nested with the plurality of second conductive bumps on the memory chip close to the substrate.”
The metes and bounds of the claimed limitation can not be determined for the following reasons: the term "close" is a relative term that renders the claim indefinite. It is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Neither the claims, nor the specification, defines how far the second pads must be to the substrate in order to be “close” to the substrate, either in terms of 0.5, 1, 2, 3, 4, 5, 10, 20, 50, 100, 250, 500, 1000 nm, or some other value. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and the claim is unclear.
Claim Interpretations
The term “nested” used in claim 11 is used repeatedly in the specification, without ever defining it. According to Merriam Webster dictionary, the pertinent definitions of the verb “to nest” that would be appropriate for semiconductor technology are “to fit compactly together or within one another” or “to pack compactly together”, and these will be used as the reasonable interpretations of this term.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 14, 17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0305226 A1 (“Tsai”).
Tsai teaches, for example:
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Tsai teaches:
11. A packaging structure of a multi-layer stacked high-bandwidth memory (see e.g. Fig. 3E, or a portion thereof in Fig. 1H), comprising:
a substrate (e.g. the structure comprising encapsulant 115, chip 112, and RDL structure 122), a plurality of memory chips (see chips 150a-150d; see HBM, para 40), and a plastic encapsulation layer (comprising e.g. encapsulant 212 as shown in Fig. 3E, and possibly encapsulant 158 and/or underfills 148 and 156), wherein:
the substrate is provided with a plurality of first conductive vias (e.g. 109, see Fig. 1H), and
a memory chip of the plurality of memory chips is provided with a plurality of second conductive vias (e.g. 136, see Fig. 1H) electrically connected with the plurality of first conductive vias;
a plurality of first conductive bumps (e.g. connectors 145, see Fig. 1H) and a plurality of second conductive bumps (e.g. connectors 147, which may be micro bumps, see e.g. para 45; see e.g. copper, para 83) sequentially disposed at positions corresponding to the plurality of second conductive vias of a surface of the memory chip facing towards the substrate (see e.g. Fig. 1H);
a plurality of pads (e.g. conductive pads 139, see e.g. para 43) disposed at positions corresponding to the plurality of second conductive vias of a surface of the memory chip facing away from the substrate (they are on the top surfaces of each of the memory chips, thus on the side thereof facing away from the substrate),
wherein a second conductive bump (e.g. 147) of the plurality of second conductive bumps and a pad (e.g. 139) of the plurality of pads on every adjacent two memory chips are nested (see claim interpretation section, above; they are in direct contact in a geometry that is well described by being “compactly together”), such that the plurality of memory chips are insulated and sequentially stacked over the substrate (the chips are insulated by underfill layers 148 from each other, stacked over the substrate); and
a plastic encapsulation layer (comprising e.g. encapsulant 212 as shown in Fig. 3E, and possibly encapsulant 158 and/or underfills 148 and 156) wrapping the plurality of memory chips and the substrate (see e.g. Fig. 3E).
14. The packaging structure according to claim 11, wherein: the plastic encapsulation layer is formed by filling a plastic sealing compound between the plurality of memory chips and between the memory chip and the substrate (see e.g. Fig. 1H, wherein 148 and 156 are between memory chips and between the memory chips and the substrate).
17. The packaging structure according to claim 11, wherein: the plurality of memory chips include a plurality of groups of memory chips, wherein each group of the memory chips includes a first memory chip and a second memory chip; the plurality of first conductive bumps and the plurality of second conductive bumps are formed at positions corresponding to the plurality of conductive vias of a surface of the first memory chip facing towards the substrate; and the plurality of pads are formed at positions corresponding to the plurality of conductive vias of a surface of the second memory chip facing away from the substrate (see Figs. 1H and 3E).
19. The packaging structure according to claim 11, further including: a plurality of solder balls (e.g. 160, see e.g. Fig. 1H and para 53), wherein the plurality of solder balls are formed on a surface of the substrate facing away from the memory chip, and the solder balls are electrically connected with the plurality of first conductive vias (see discussion of electrical connection in e.g. para 53, 45, 49, 52, etc.).
20. The packaging structure according to claim 11, further including: a plurality of second pads (e.g. 130 as labeled in Fig. 1G, which is a pad touching 155; 155 is equivalent to 147 in the discussion of claim 11) disposed on a surface of the substrate facing towards the memory chip, wherein the plurality of second pads are nested with the plurality of second conductive bumps on the memory chip close to the substrate (see e.g. Fig. 1G).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of US 2013/0134588 A1 (“Yu”).
Re claims 12-13, Tsai teaches claim 11, but does not explicitly further teach: wherein: a protrusion is formed on a side of the pad facing towards the second conductive bump, and a trench is formed on a side of the second conductive bump facing towards the pad, wherein the protrusion is inserted into the trench (claim 13); or
The packaging structure according to claim 12, wherein: the second conductive bump has a columnar structure (claim 13).
Yu teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Tsai wherein: a protrusion is formed on a side of the pad facing towards the second conductive bump (see e.g. stud bulb 18, which protrudes upward from pad protection layer 16), and a trench is formed on a side of the second conductive bump facing towards the pad (see wherein 28 extends downward, but has a “trench” in its middle), wherein the protrusion is inserted into the trench (see e.g. Fig. 8) (claim 13); and
The packaging structure according to claim 12, wherein: the second conductive bump has a columnar structure (see e.g. para 41 and e.g. Figs. 6-7, wherein 26 is reflowed into a generally hemispherical shape, and then connected to 16/18/20 and surrounds 16/18/20, thus forming a generally columnar shape) (claim 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Yu to the invention of Tsai. The motivation to do so is that the combination produces the predictable results of forming the pad out of various layers that provide protection, having a stud bulb thereon which can be prevented from oxidation, see e.g. para 39, which can be connected to a reflowed solder to provide a robust electrical and mechanical connection, see e.g. para 41).
Re claim 18, Tsai teaches claim 11, but does not explicitly further teach: wherein: a melting point of the first conductive bump is greater than a melting point of the second conductive bump.
Yu teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Tsai wherein a melting point of the first conductive bump is greater than a melting point of the second conductive bump (see e.g. Fig. 7 and para 41, 40, etc., wherein material 26 is the solder, and it reflows during a soldering process, whereas the pads and other connectors 24, 20, 18, 16, and 12 do not reflow; hence the solder has the lowest melting point; in Tsai, Fig. 1H, it is clear that connector 145 should not reflow whereas 147 is made of solder and thus should reflow, and thus second connector 147 has a lower melting point than that of 145).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Yu to the invention of Tsai. The motivation to do so is that the combination produces the predictable results of forming the pad out of various layers that provide protection, having a stud bulb thereon which can be prevented from oxidation, see e.g. para 39, which can be connected to a reflowed solder to provide a robust electrical and mechanical connection, see e.g. para 41).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Re claim 15, Tsai teaches claim 11, as discussed above, and further teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein: both a first conductive via of the plurality of conductive vias and a second conductive vias of the plurality of second conductive vias include a through-silicon via (see wherein the substrate 102 may be silicon in e.g. para 14, and wherein the substrates 135 of the memory chips may be semiconductors).
While the specific “semiconductor” material of the memory chips has not been disclosed, one of ordinary skill in the art would have found it obvious to use silicon for many reasons. First, the logic chip is made of silicon. Second, silicon is ubiquitous in the semiconductor industry and is well-known to be used in memory chips.
Applicant has not disclosed that the claimed material (silicon, in the “through-silicon vias”) is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of US 2020/0135677 A1 (“Chang”).
Tsai teaches claim 11, but does not explicitly further teach: wherein the second conductive bump is made of a material including tin.
Chang teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Tsai wherein the second conductive bump is made of a material including tin (see e.g. para 29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Chang to the invention of Tasi. The motivation to do so is that the combination produces the predictable results of using a “suitable metallic bump” (Tsai, para 45) that specifically includes tin (see Chang, e.g. para 29), as it is a lead-free solder, which is well-known to be good for the environment; and it is formed of alloys like Sn-Ag or Sn-Ag-Cu which can be formed by plating (see e.g. para 29).
Applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2021/0118803 A1 (“Park”) teaches multilayered bumps on chips (see e.g. Fig. 2).
US 2020/0203315 A1 (“Shih”) teaches multilayered bumps on chips between chips (see e.g. Fig. 8).
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
Prosecution Insights