DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-10 are pending in this application.
Applicant’s election without traverse of Group II (claims 8-10) in the reply filed on September 8, 2026, is acknowledged.
Claims 1-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 8, 2026.
The Examiner notes that claims 1-7 are withdrawn and claims 8-10 are examined.
Priority
Acknowledgement is made to claims of the benefit of priority from Japanese Patent Application No. 2023-159965, filed on September 25, 2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 31, 2024, and September 29, 2026, are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2015/0144995 A1).
With respect to claim 8, Takahashi teaches in Fig. 18:
A method for manufacturing a semiconductor device, the method comprising:
forming a semiconductor part, the semiconductor part including a first region, a second region, and a third region, the third region being located between the first region and the second region (see annotated Fig. 18 below),
the semiconductor part having a first surface (top) and a second surface (bottom) opposite to the first surface, the first region including a first sub-region (n-type drift layer 1) of a second conductivity type (n), a second sub-region (p-type base layer 2) of a first conductivity type (p) located on the first sub-region (1), a third sub-region (n-type emitter layer 3) of the second conductivity type (n) located on the second sub-region,
and a gate electrode (trench gate electrode 5) facing the second sub-region via a gate insulating layer (gate insulating film 6) in a second direction (left/right) connecting the first region and the second region,
the second region including the first sub-region (1), a fourth sub-region (p-type anode layer 7) of the first conductivity type located on the first sub-region,
and a conductive part (dummy trench gate electrode 19) facing the fourth sub-region via an insulating layer (dummy gate insulating film 20) in the second direction,
the third region including the first sub-region (1);
forming a first electrode (emitter electrode 9) on the first surface of the first region, the second region, and the third region;
forming a fifth sub-region (N+ type buffer layer 14) on the second surface, the fifth sub-region having a higher second-conductivity-type impurity concentration than the first sub-region (concentration shown in Fig. 1 shows that 14 has a higher concentration than 1);
coating a first resist onto the second surface; ([0068] “a pattern is formed by using a general photolithography technology”),
implanting at least one selected from the group consisting of oxygen, nitrogen, and carbon into a portion of the fifth sub-region via the first opening; (and oxygen is injected to a predetermined spot by using an impurity injection technology”)
and removing the first resist that was coated onto the first region and the second region ([0068] “After the pattern is removed, by applying heat treatment, the embedded oxide film 29 is formed.”)
The Examiner notes that the formation of the resist is described by Takahashi as “a general photolithography technology” and does not explicitly teach that it is formed by “coating a first resist onto the second surface; removing a portion of the first resist located under the third region to form an opening in the first resist;” The Examiner takes official notice that the use of a photoresist as a mask in which portions of a resist is removed from regions that are etched are well known in the art. It would have been obvious to one of ordinary skill in the art at the time of the invention to use a photoresist patterning technique that meets the claimed limitation because the known technique of using a photoresist by applying a layer and removing portions before etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 9, Takahashi further teaches:
forming a sixth sub-region (p type collector layer 11) of the first conductivity type (p) located under the fifth sub-region (14) by implanting an impurity of the first conductivity type to the second surface on which the first resist was removed (Fig. 9 shows the formation step, 25 is formed where the resist pattern 23 is not present).
It would be obvious to further modify Takahashi such that the p layer 25 is formed where the first resist pattern is removed because the known technique of using a photoresist by applying a layer and removing portions before etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 10, Takahashi further teaches:
coating a second resist (resist pattern 26) onto the second surface after forming the sixth sub-region,
implanting an impurity of the second conductivity type to the sixth sub-region of the second region via the second opening ([0058] “ the n-type impurities are injected at a position which is shallow from the back surface so as to form an n.sup.+-type cathode layer forming region 28.”);
and removing the second resist ([0058] “removing an injection pattern”).
Takahashi does not state the method of forming the second resist and does not explicitly teach:
The Examiner notes that the formation of the resist is described by Takahashi as “a general photolithography technology” and does not explicitly teach that it is formed by “the second resist being located under the first region, the second region, and the third region;
removing a portion of the second resist that was coated under the second region to form a second opening;” The Examiner takes official notice that the use of a photoresist as a mask in which portions of a resist is removed from regions that are etched are well known in the art. It would have been obvious to one of ordinary skill in the art at the time of the invention to use a photoresist patterning technique that meets the claimed limitation because the known technique of using a photoresist by applying a layer and removing portions before etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
