DETAILED ACTION
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7,11-16,18-20 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by GRUDDANTI (US 20240186994 A1).
Regarding claim 1, GRUDDANTI discloses a device [Fig. 2] comprising:
a first die [Die 202a] comprising:
a clock circuit [PLL 212] configured to output a first clock signal and a second clock signal [clock signals 214 and 216];
and
a control circuit [Tx BLOCK 204A] configured to receive the first clock signal from the clock circuit and the second clock signal from the clock circuit; and
a second die stacked over the first die [0011, 0029: the first die 202a and the second die 202b are chiplets];
wherein the control circuit configured to:
forward data to the second die based on the first clock signal [abstract: Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die][0009][0024][0030: The Rx blocks 206a, 206b each include a plurality of I/O connection points allocated or dedicated to receiving signals (e.g., data signals or clock signals) from the aforementioned Tx blocks][0044-0050]; and
forward the second clock signal to the second die [0009] [0044: Such transmission of the strobe signal 216 from the first die 202a to the second die 202b implements a “forwarded” or a “source-synchronous” clock signal. Use of the strobe signal 216 as a source-synchronous clock signal for the second die 202b allows the semiconductor package 200 to support higher data rates for transmitting data between the first die 202a and the second die 202b] [0030] [0045-0050].
PNG
media_image1.png
561
581
media_image1.png
Greyscale
Regarding claim 2, GRUDDANTI discloses the device of claim 1, wherein the second die further comprises a clock tuning circuit for tuning the second clock signal for a data circuit of the second die [0045-0049: strobe receiver].
Regarding claim 3, GRUDDANTI discloses the device of claim 2, wherein the clock tuning circuit tunes the second clock signal independently from the first clock signal [0045-0049: strobe receiver][Fig.2].
Regarding claim 4, GRUDDANTI discloses the device of claim 1, wherein the control circuit receives the second clock signal directly from the clock circuit of the first die via an independent branch of a clock tree of the first die that is separated from the first clock signal [0045-0049: clock signal 216][Fig.2].
Regarding claim 5, GRUDDANTI discloses the device of claim 4, wherein a branching point of the independent branch is closer to a root of the clock tree than the control circuit [0045-0049: clock signal branches 214, 216][Fig.2].
Regarding claim 6, GRUDDANTI discloses the device of claim 4, wherein a branching point of the independent branch is closer to the control circuit than a root of the clock tree [0045-0049: clock signal branches 214, 216] [Fig.2].
Regarding claim 7, GRUDDANTI discloses the device of claim 1, wherein the control circuit uses the first clock signal to synchronize with a data circuit of the first die [abstract: Different connection paths transmit data signals from the first die to the second die based on the local clock signal] [0009: synchronous] [0044-0050].
Regarding claim 11, GRUDDANTI discloses the device of claim 1, wherein the control circuit forwards the second clock signal using a through-silicon via (TSV) [0013: The connection paths can include conductive traces, wires, pins, vias, or other conductive couplings as can be appreciated][0011,0029,0032: A bridge die is a die of semiconductive material (e.g., silicon) onto which the connection paths are fabricated].
Regarding claim 12, GRUDDANTI discloses a system [Figs 2 and 6] comprising:
a memory [0054, Fig. 6, RAM 604 or data storage 612]; and
a processor [0054, Fig. 6, semiconductor package 200 may be implemented as at least one processor 602] comprising:
a first die [die 202a] comprising:
a clock circuit [PLL 212] configured to output a clock signal using at least a first branch and a second branch [clock signals 214 and 216];
a data circuit for holding data from the memory [0054 and Fig. 6, data operations between RAM 604 (or data storage 612) and processor 602]; and
a control circuit [Tx BLOCK 204A] that receives the clock signal from the first branch and the clock signal from the second branch, and synchronizes with the data circuit using a modified clock signal based on the first branch ; and a second die [die 202b] stacked over the first die [0011, 0029: the first die 202a and the second die 202b are chiplets]; wherein the control circuit is configured to: forward data from the data circuit to the second die; and forward an unmodified clock signal from the second branch to the second die [abstract: Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die][0030: The Rx blocks 206a, 206b each include a plurality of I/O connection points allocated or dedicated to receiving signals (e.g., data signals or clock signals) from the aforementioned Tx blocks][0044-0050] [0009] [0044: Such transmission of the strobe signal 216 from the first die 202a to the second die 202b implements a “forwarded” or a “source-synchronous” clock signal. Use of the strobe signal 216 as a source-synchronous clock signal for the second die 202b allows the semiconductor package 200 to support higher data rates for transmitting data between the first die 202a and the second die 202b].
Regarding claim 13, GRUDDANTI discloses the system of claim 12, wherein the second die further comprises a clock tuning circuit for tuning the unmodified clock signal independently from the modified clock signal [0045-0049: strobe receiver].
Regarding claim 14, GRUDDANTI discloses the system of claim 12, wherein the control circuit receives the unmodified clock signal directly from the clock circuit of the first die via the second branch that comprises an independent branch of a clock tree of the first die that is separated from the first branch [0045-0049: clock signals 214 and 216][Fig.2].
Regarding claim 15, GRUDDANTI discloses the system of claim 14, wherein a branching point of the independent branch is closer to a root of the clock tree than the control circuit [0045-0049: clock signal branches 214, 216].
Regarding claim 16, GRUDDANTI discloses the system of claim 14, wherein a branching point of the independent branch is closer to the control circuit than a root of the clock tree [0045-0049: clock signal branches 214, 216].
Regarding claim 18, GRUDDANTI discloses a method comprising:
receiving, by a control circuit of a first die from a clock circuit of the first die, a first clock signal from the clock circuit and a second clock signal from the clock circuit; synchronizing a data circuit of the first die with the control circuit of the first die using the first clock signal; forwarding the second clock signal from the control circuit of the first die to a clock tuning circuit of a second die stacked near the first die; and tuning the second clock signal with the clock tuning circuit independently of the first clock signal [0009] [0044: Such transmission of the strobe signal 216 from the first die 202a to the second die 202b implements a “forwarded” or a “source-synchronous” clock signal. Use of the strobe signal 216 as a source-synchronous clock signal for the second die 202b allows the semiconductor package 200 to support higher data rates for transmitting data between the first die 202a and the second die 202b] [abstract: Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die][0009][0024] [0030: The Rx blocks 206a, 206b each include a plurality of I/O connection points allocated or dedicated to receiving signals (e.g., data signals or clock signals) from the aforementioned Tx blocks] [0045-0050] [Fig.2].
Regarding claim 19, GRUDDANTI discloses the method of claim 18, further comprising:
forwarding the second clock signal to a second clock tuning circuit of a third die; and
tuning the second clock signal with the second clock tuning circuit independently of the
first die and the second die [0045-0049: strobe receiver][Fig.2].
Regarding claim 20, GRUDDANTI discloses the method of claim 18, wherein the second clock signal corresponds to an unmodified clock signal from a branch directly from the clock circuit [0045-0049: clock signal 216] [Fig.2].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over GRUDDANTI (US 20240186994 A1) and in view of Berenbaum et al (US 20130297829 A1).
Regarding claim 8, GRUDDANTI does not disclose a third die stacked over the second die, wherein the second die comprises a second control circuit configured to forward the second clock signal to the third die.
Berenbaum discloses a third die stacked over the second die, wherein the second die comprises a second control circuit configured to forward the second clock signal to the third die [Fig.3 and 0029: the SPI slave 322 of the slave device 320 is clocked by the SPI clock signal received from the SPI master 312 that operates in the master's clock domain. Similarly, the SPI slave 332 of the slave device 330 is clocked by the SPI clock signal forwarded by the SPI slave 322].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of GRUDDANTI and Berenbaum together because they both directed to forward the clock signal to the next chip. Berenbaum’s disclosing of the second die comprises a second control circuit configured to forward the second clock signal to the third die would allow GRUDDANTI to avoid data transfer over run or under run at each chip because the source clock and the forwarding claim are toggled at the same rate.
Regarding claim 9, Berenbaum discloses the device of claim 8, wherein the third die further comprises a clock tuning circuit for tuning the second clock signal [Fig. 3 and 0029].
Regarding claim 10, Berenbaum discloses the device of claim 9, wherein the clock tuning circuit tunes the second clock signal independently from the first die and the second die [Fig. 3 and 0029].
Claim 17 is taught by Berenbaum for the same reasons as disclosed in claim 8.
Response to Arguments
Applicant’s arguments filed on 06/22/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHIL K NGUYEN/ Primary Examiner, Art Unit 2176
Prosecution Insights