Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over “Kyozuka” (US 2023/0300987) in view of “Lee” (US 2022/0151061).
Regarding claim 1, Kyozuka discloses 1. A circuit board, comprising: a substrate having a first surface and a second surface facing each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity penetrating in a direction perpendicular to the first surface (Fig. 5B, [0070]-[0071]; solder resist layer 30);
a first wiring pattern embedded in the insulating layer on the first surface to enable signal transmission (Fig. 5B, [0070]-[0071]; power supply pattern 29);
and a first reinforcement pattern embedded in the insulating layer on the first surface, disposed around the cavity, and separated from the first wiring pattern (Fig. 5B, [0070]-[0071]; reinforcing metal layer 22A).
Kyozuka does not disclose the reinforcement pattern to be spaced apart from an edge of the cavity.
Lee discloses the reinforcement pattern to be spaced apart from an edge of the cavity (Fig. 1, [0036]; reinforcing pattern 50).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board with Lee’s reinforcing pattern in order to prevent or delay a crack in the circuit pattern that may occur, as suggested by Lee at [0040].
Regarding claim 2, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 2. The circuit board of claim 1, wherein: the first reinforcement pattern includes metal (Fig. 5B, [0070]-[0071]; reinforcing metal layer 22A).
Regarding claim 3, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 3. The circuit board of claim 1, wherein: the first reinforcement pattern is electrically isolated (Fig. 1, [0037] the reinforcing metal layer 22 is separated from the power supply pattern 29).
Regarding claim 4, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 4. The circuit board of claim 1, wherein: the first reinforcement pattern is covered with the insulating layer (Fig. 5B, [0070]-[0071]; reinforcing metal layer 22A and solder resist layer 30).
Kyozuka does not disclose the reinforcement pattern is not exposed to the cavity.
Lee discloses the reinforcement pattern is not exposed to the cavity (Fig. 1, [0036]; reinforcing pattern 50).
Regarding claim 5, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 5. The circuit board of claim 1, wherein: the first reinforcement pattern has the same height as the first wiring pattern (Fig. 1, [0037] the reinforcing metal layer 22 and the power supply pattern 29 have the same height).
Regarding claim 6, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 6. The circuit board of claim 1, wherein: the first wiring pattern is spaced apart from the first reinforcement pattern in a direction away from the cavity (Fig. 1, [0037] the power supply pattern 29 is apart from the reinforcing metal layer 22 away from the cavity).
Regarding claim 11, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 11. The circuit board of claim 1, wherein: the first reinforcement pattern includes a plurality of reinforcement pads spaced apart from each other along the edge of the cavity (Fig. 12).
Regarding claim 12, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 12. The circuit board of claim 1, wherein: the first reinforcement pattern is configured to continuously connect along the edge of the cavity and surround the cavity (Fig. 9).
Regarding claim 13, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka discloses 13. The circuit board of claim 1, wherein: the cavity includes four sides, and the first reinforcement pattern includes reinforcement pads disposed on each of the four sides (Fig. 10).
Claims 7-10 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kyozuka in view of Lee and “Hsu” (US 2008/0151518).
Regarding claim 7, Kyozuka in view of Lee discloses the claimed invention as applied to claim 1, above.
Kyozuka does not disclose the limitations of claim 7.
Lee discloses a second wiring pattern disposed on the insulating layer on the second surface to enable signal transmission; and a via embedded in the insulating layer and connecting the first wiring pattern and the second wiring pattern to each other (Fig. 1, [0045]; via hole 60 and land patterns 62).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board, as modified by Lee, with a second reinforcement pattern and second wiring pattern, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Furthermore, Hsu, Fig. 2, [0006] and [0013], teaches the circuit board is structurally reinforced by the plurality of the metal layers so as to enhance the bending strength of the circuit board structure.
Regarding claim 8, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 7, above.
Kyozuka discloses 8. The circuit board of claim 7, wherein: the reinforcement pattern protrudes above the surface to have the same height as the wiring pattern (Fig. 1, [0037] the reinforcing metal layer 22 and the power supply pattern 29 have the same height).
Kyozuka does not disclose the second reinforcement pattern and the second wiring pattern.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board, as modified by Lee and Hsu, with a second reinforcement pattern and second wiring pattern, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Furthermore, Hsu, Fig. 2, [0006] and [0013], teaches the circuit board is structurally reinforced by the plurality of the metal layers so as to enhance the bending strength of the circuit board structure.
Regarding claim 9, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 7, above.
Kyozuka discloses 9. The circuit board of claim 7, wherein: the wiring pattern is spaced apart from the reinforcement pattern in a direction away from the cavity (Fig. 1, [0037] the power supply pattern 29 is apart from the reinforcing metal layer 22 away from the cavity).
Kyozuka does not disclose the second reinforcement pattern and the second wiring pattern.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board, as modified by Lee and Hsu, with a second reinforcement pattern and second wiring pattern, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Furthermore, Hsu, Fig. 2, [0006] and [0013], teaches the circuit board is structurally reinforced by the plurality of the metal layers so as to enhance the bending strength of the circuit board structure.
Regarding claim 10, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 7, above.
Kyozuka does not disclose the limitations of claim 10.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board, as modified by Lee and Hsu, to arrange the second reinforcement pattern overlapping the first reinforcement pattern since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Such an arrangement would have required routine experimentation.
Regarding claim 14, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 7, above.
Kyozuka discloses 14. The circuit board of claim 7, wherein: the first reinforcement pattern extends from the first surface and into the insulating layer (Fig. 5B).
Regarding claim 15, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 14, above.
Kyozuka does not disclose the limitations of claim 14.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board, as modified by Lee and Hsu, to arrange the second reinforcement pattern offset from the first reinforcement pattern since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Such an arrangement would have required routine experimentation.
Regarding claim 16, Kyozuka discloses 16. An electronic device package, comprising: a substrate having a first surface and a second surface facing each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity penetrating in a direction perpendicular to the first surface (Fig. 5B, [0070]-[0071]; solder resist layer 30);
a first wiring pattern embedded in the insulating layer on the first surface to enable signal transmission (Fig. 5B, [0070]-[0071]; power supply pattern 29);
a first reinforcement pattern embedded in the insulating layer on the first surface, disposed around the cavity, and separated from the first wiring pattern (Fig. 5B, [0070]-[0071]; reinforcing metal layer 22A);
a redistribution layer disposed on the first surface of the substrate (Fig. 15, [0137], [0143]; interconnect layer 112).
Kyozuka does not disclose the reinforcement pattern to be spaced apart from an edge of the cavity and an electronic device accommodated in the cavity and connected to the redistribution layer.
Lee discloses the reinforcement pattern to be spaced apart from an edge of the cavity (Fig. 1, [0036]; reinforcing pattern 50).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board with Lee’s reinforcing pattern in order to prevent or delay a crack in the circuit pattern that may occur, as suggested by Lee at [0040].
Hsu discloses an electronic device accommodated in the cavity and connected to the redistribution layer (Fig. 2, [0026]; semiconductor chip 14).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kyozuka’s circuit board, as modified by Lee, with Hsu’s chip in order to embed an electronic component into a packaged substrate so as to conform with the trend of miniaturization, as suggested by Hsu at [0002].
Regarding claim 17, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 16, above.
Kyozuka discloses 17. The electronic device package of claim 16, further comprising: an insulating protective layer disposed between the first surface of the substrate and the redistribution layer to cover the first reinforcement pattern (Fig. 15, [0138]; insulating layer 123).
Regarding claim 18, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 16, above.
Kyozuka discloses 18. The electronic device package of claim 16, wherein: the first reinforcement pattern is electrically isolated (Fig. 1, [0037] the reinforcing metal layer 22 is separated from the power supply pattern 29).
Regarding claim 19, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 16, above.
Kyozuka discloses 19. The electronic device package of claim 16, wherein: the first reinforcement pattern is covered with the insulating layer (Fig. 5B, [0070]-[0071]; reinforcing metal layer 22A and solder resist layer 30).
Kyozuka does not disclose the reinforcement pattern is not exposed to the cavity.
Lee discloses the reinforcement pattern is not exposed to the cavity (Fig. 1, [0036]; reinforcing pattern 50).
Regarding claim 20, Kyozuka in view of Lee and Hsu discloses the claimed invention as applied to claim 16, above.
Kyozuka discloses 20. The electronic device package of claim 16, wherein: the first wiring pattern is spaced apart from the first reinforcement pattern in a direction away from the cavity (Fig. 1, [0037] the power supply pattern 29 is apart from the reinforcing metal layer 22 away from the cavity).
Conclusion
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/STANLEY TSO/Primary Examiner, Art Unit 2847