DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2008/0173792 A1) (“Yang”), in view of Hanai et al. (US 2012/0217607 A1) (“Hanai”).
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Regarding claim 1, Yang teaches at least in figures 2, and 4-6, and Examiner’s annotated figure 4 above:
a first semiconductor substrate (2) including (detailed below):
a first region (A) having a photoelectric conversion section (6), and
a via portion (D),
wherein the via portion (D) includes a first via and a second via (there are at least two Ds as indicated by the two arrows extending from “D=vias” in Examiner’s figure above),
wherein the first via is adjacent to the second via (all Ds are adjacent) in a plan view (while a cross-sectional view is shown it would be obvious that a plan view would show the same thing);
a second region (B) adjacent to the first region (A);
a connection portion (E) disposed at the second region (B),
a second semiconductor substrate (30/28),
wherein the connection portion (E) electrically couples the first semiconductor substrate (2) to the second semiconductor substrate (30/28) in a stacked configuration (They are so stacked)
Yang does not teach:
wherein:
the connection portion includes a first electrode and a second electrode,
the first electrode is adjacent to the second electrode in the plan view, and
a first distance between the first via and the second via is less than a second distance between the first electrode and the second electrode.
Hanai teaches at least in figures 1-3B:
wherein:
the connection portion (figure 3A-3B) includes a first electrode and a second electrode,
the first electrode (a first 13) is adjacent to the second electrode (a second 13) in the plan view (figure 2).
It would have been obvious to one of ordinary skill in the art to combine Hanai with Yang as Yang does not provide all the details for the how the secondary substrates/chips connect to the primary substrate. Yang instead gives more of a global view of the process. Therefore, it would have been obvious to one of ordinary skill in the art to search for a reference with provides more details in how to connect the secondary substrates to the primary substrates. This search would have led to Hanai.
Regarding the limitations below,
a first distance between the first via and the second via (Yang Ds) is less than a second distance between the first electrode and the second electrode (Hanai 13) (This limitation is not expressly shown. However, it would have been obvious that the vias would be closer together than the electrodes. This is because the vias are internal to the semiconductor device, and thus are generally known in the art to be formed closely to take advantage of photolithography processing parameters such as iso/dense bias. Further, it is known in the art that electrodes connecting to soldered chips need to be spaced further apart than vias as they need to take into account the space for lead/BGA and solder to connect said devices.).
Regarding claim 2, The prior art teaches:
wherein the first semiconductor substrate (Yang 2) further includes a wiring layer (Hanai R0) provided on a surface of the first semiconductor substrate (Yang 2; Hanai Figure 1), and
the via portion (Yang D) penetrates the first semiconductor substrate (Yang 2) and is connected to a wiring provided in the wiring layer (Hanai R0).
Regarding claim 3, The prior art teaches:
wherein a cross-section area of a portion of the via portion connected to the wiring in the wiring layer is less than an area of the connection portion (This is shown in Examiner’s Yang annotated figure 4 above).
Regarding claims 4-5,
While the limitations of claim 4 are not shown because a plan view is not shown in Yang, it would have been obvious that total area of 28/30 is less than the total area of 2 as 28/30 sit on top of 2.
Regarding claim 6, the prior art teaches:
wherein the connection portion (Yang E) has a first electrode portion (a portion of Hanai 13) and a metal layer portion (Hanai 33), and
the second semiconductor substrate (Yang 28/30) is mounted on the first semiconductor substrate (Yang 2) by connecting the connection portion (Yang E) and a micro bump (Hanai 3000b) provided on the second semiconductor substrate (Yang 28/30; Hanai 3000).
Regarding claim 7, the prior art teaches:
wherein the connection portion (Yang E) is formed in a wiring layer provided at a surface side of the first semiconductor substrate (Yang E is so formed), and
a metal layer (Hanai 13) in the wiring layer (Hanai 13) is between the connection portion (Yang E) and the first semiconductor substrate (Yang 2).
Regarding claim 8, the prior art teaches:
wherein the first electrode (Hanai 13) , the connection portion (Yang E), and a connection wiring (based upon claim 1 the first electrode is part of the connection wiring; Hanai 13) provided at an end of a surface side of the via portion (Yang D; Hanai 12b) are formed in a wiring layer (Based upon Applicant’s disclosure the wiring layer 63 includes the connection portion and the first electrode 54; The prior art teaches these same elements as shown above) and provided at a surface side of the first semiconductor substrate (Yang 2), and
a groove that reduces a step of the connection portion relative to the connection wiring and the electrode is formed in a region directly below the connection portion in the first semiconductor substrate (As far as Examiner understands this limitation Applicant is claiming the groove on top of element 55. Hanai teaches there is a groove around T1 which reduces the step of the connection portion. Applicant does not claim what the connection portion consist of).
Response to Arguments
Applicant's arguments filed October 15, 2025 have been fully considered but they are not persuasive.
Applicant asserts two conclusory arguments against the references. The arguments are conclusory because Applicant’s arguments merely state the prior art doesn’t teach certain limitations. Examiner’s response is contrary to Applicant’s conclusion statement, in that Examiner’s conclusory statement is the prior art does teach the limitations.
More specifically, Applicant’s first argument is that neither Yang nor Hanai teach the via portion includes a first via and a second via. This is not persuasive. As shown in the rejection of claim 1, and in Examiner’s figure above, one can see that there are two arrows extending from D. Each of these arrows is pointing to a via. Therefore, this argument is unpersuasive.
The second argument is that the prior art references do not teach the connection portion and its corresponding limitations. This argument is unpersuasive for the reasons stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/Primary Examiner, Art Unit 2898