DETAILED ACTION
This Office Action is in response to Applicant’s application 18/680,460 filed on May 31, 2024 in which claims 1 to 24 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on May 31, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on May 31, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
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Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2012/0319233 (Feilchenfeld).
Regarding claim 1 Felichenfeld discloses at annotated Figure 29 a semiconductor device, comprising:
a semiconductor substrate, 10 [0053], including a bipolar junction transistor (BJT) region, as annotated and shown as ‘B’ in Figure 2 [0055], and a complementary field effect transistor (CFET) region, as annotated and shown as ‘C’ in Figure 2 [0055];
a pad layer, 51 described as silicon oxide at [0055], over the semiconductor substrate in the BJT region, as shown;
a dielectric layer, 52 described as silicon nitride at [0055] over the etch stop layer in the BJT region, as shown;
a BJT on the semiconductor substrate in the BJT region, e.g. 30 is the collector, 60 is the base and 91 is the emitter, at least a first portion of the BJT, as shown, being in an opening through the pedestal dielectric layer and the etch stop layer, as annotated and shown, at least a second portion of the BJT further being over the pedestal dielectric layer, as annotated and shown; and
a field effect transistor (FET), as annotated and described at [0054], on the semiconductor substrate in the CFET region, as shown.
Feilchenfeld does not explicitly teach the pad 51 is an etch stop layer. However Examiner takes the position that silicon oxide has the properties of being an etch stop layer. For example, in a (very old) LOCOS process, silicon nitride on a pad oxide was patterned using a plasma process, i.e. stopping the etch on the silicon dioxide pad followed by field oxidation, i.e. local oxidation of silicon. Likewise pad 52 appears to have the structure of a pedestal dielectric layer. Accordingly, Examiner takes the position that pad 51 and pad 52 have the structure and properties of an etch stop layer and a pedestal dielectric layer and so meet the claim.
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2 the prior art fails to disclose the device of claim 1, further comprising an oxidation layer on the semiconductor substrate in the BJT region, the etch stop layer being over the oxidation layer.
Regarding claim 3 the prior art fails to disclose the device of claim 1, wherein: the BJT comprises: a collector layer on the semiconductor substrate, the collector layer being in the opening through the pedestal dielectric layer and the etch stop layer; a base layer on the collector layer, the base layer being over the pedestal dielectric layer; and an emitter layer on the base layer.
Claims 4-8 depend directly or indirectly on claim 3 and are allowable on that basis.
Claims 9-24 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 9 the prior art fails to disclose a method, comprising: forming a gate layer over a semiconductor substrate in a bipolar junction transistor (BJT) region and a complementary field effect transistor (CFET) region; patterning the gate layer into a gate electrode of a field effect transistor (FET) in the CFET region; forming a first etch stop layer conformally over the semiconductor substrate in the BJT region and the CFET region and over the gate electrode; forming a collector layer on the semiconductor substrate and in an opening through the first etch stop layer in the BJT region; forming a base layer on the collector layer and at least partially over the first etch stop layer; and forming an emitter layer on the base layer.
Claims 9-19 depend directly or indirectly on claim 9 and are allowable on that basis.
Regarding claim 20 the prior art fails to disclose a method, comprising: forming a gate layer over a semiconductor substrate in a bipolar junction transistor (BJT) region and a complementary field effect transistor (CFET) region; patterning the gate layer in the CFET region into a gate electrode of a field effect transistor (FET) in the CFET region; forming a first etch stop layer conformally in the CFET region and the BJT region, the first etch stop layer being along a side of the gate electrode and over the gate electrode; forming a collector layer on the semiconductor substrate and through an opening in the first etch stop layer in the BJT region; forming a material of a base layer over the collector layer and over the first etch stop layer; forming a material of an emitter layer over the base layer; patterning the material of the emitter layer into the emitter layer in the BJT region; and patterning the material of the base layer into the base layer in the BJT region.
Claims 21-24 depend directly or indirectly on claim 20 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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