DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5.31.2024 is being considered by the examiner.
Examiner Note
Claims may be separately rejected below under different prior art to show unpatentability of the claims.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Johnson et al. (US 20020018355 A1).
Regarding claim 1, Johnson discloses a semiconductor device (Fig. 5) comprising:
a plurality of word lines (conductors 3/5/7) extending in a first direction (W-E);
a plurality of bit lines (conductors 4/6) extending in a second direction (S-N or into the page; see Fig. 4(a)) crossing the first direction;
a plurality of memory cells (pillars 3/4/5/6) in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect; and
a semiconductor element (pillars 1/2; MPEP 2111) connected (indirectly at least) to at least one of the plurality of word lines and the plurality of bit lines, the semiconductor element (Fig. 6(a)) including a first active pattern (40, P+ Poly) and a second active pattern (41, N Poly) overlapping the first active pattern along a height direction (Up-Down) perpendicular to the first and second directions (Figs. 5 and 6(a)).
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Regarding claim 2, Johnson discloses the semiconductor device of claim 1, wherein the semiconductor element (pillars 1/2) overlaps the plurality of memory cells along the height direction (Up-Down, Fig. 5).
Regarding claim 5, Johnson discloses the semiconductor device of claim 1, wherein
the first active pattern (40, P+ Poly) of the semiconductor element has a first type conductivity, and the second active pattern (41, N Poly) has a second type conductivity different from the first type conductivity (P vs N).
Regarding claim 6, Johnson discloses the semiconductor device of claim 5, wherein
the first type conductivity (of 40, P+ Poly) is P-type and the second type conductivity (of 41, N Poly) is N-type.
Regarding claim 8, Johnson discloses the semiconductor device of claim 1, wherein
the first active pattern (40, P+ Poly) of the semiconductor element includes a plurality of first sheet patterns (one in pillar 1, another in pillar 2; Fig. 5 above), and the second active pattern (41, N Poly) of the semiconductor element includes a plurality of second sheet patterns (one in pillar 1, another in pillar 2; Fig. 5 above).
Regarding claim 9, Johnson discloses the semiconductor device of claim 8, wherein
the plurality of first sheet patterns (plural 40; Fig. 5 above) are stacked and spaced apart from each other along the height direction (Up-Down), and the plurality of second sheet patterns (plural 41; Fig. 5 above) are stacked and spaced apart from each other along the height direction (Up-Down).
Regarding claim 10, Johnson discloses the semiconductor device of claim 9, wherein the first active pattern (40, P+ Poly) of the semiconductor element has a first type conductivity (P), and the second active pattern (41, N Poly) has a second type conductivity (N) different than the first type conductivity.
Regarding claim 11, Johnson discloses the semiconductor device of claim 10,wherein
the first type conductivity is P-type (40, P+ Poly) and the second type conductivity is N-type (41, N Poly).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20020018355 A1) in view of Nagashima (US 20100187591 A1).
Regarding claim 3, Johnson fails to disclose the semiconductor device of claim 2, wherein
each of the plurality of memory cells includes
a first electrode contacting one of the plurality of word lines,
a second electrode contacting one of the plurality of bit lines, and
a switch memory between the first electrode and the second electrode.
Nagashima discloses (Fig. 3B) wherein
each of the plurality of memory cells (MCx) includes
a first electrode (EL2) contacting one of the plurality of word lines (WLx),
a second electrode (BM) contacting one of the plurality of bit lines (BLx), and
a switch memory (VR) between the first electrode and the second electrode.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Nagashima in Johnson and arrive at the claimed invention so as to provide means for electrically addressing memory cells since the use of conventional materials (memory materials in this case) to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Johnson/Nagashima discloses (Fig. 3B) the semiconductor device of claim 3, wherein
the first electrode (EL2), the switch memory (VR), and the second electrode (BM) overlap each other along the height direction.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 20190172502 A1).
Regarding claim 1, Jeong discloses a semiconductor device comprising:
a plurality of word lines (130-x) extending in a first direction (Figs. 7-8);
a plurality of bit lines (160-x) extending in a second direction crossing the first direction (Figs. 7 & 9);
a plurality of memory cells (MC, Figs. 10-14) in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect ([0035]); and
a semiconductor element (DR_WLx and/or DR_BLx, Figs. 8-9) connected to at least one of the plurality of word lines and the plurality of bit lines, the semiconductor element including a first active pattern (GL; active element of a transistor) and a second active pattern (SD+channel; active element of a transistor) overlapping the first active pattern along a height direction (vertical) perpendicular to the first and second directions (Figs. 7-9).
Regarding claim 2, Jeong discloses the semiconductor device of claim 1, wherein
the semiconductor element (DR_WLx and/or DR_BLx, Figs. 8-9) overlaps (at least partially) the plurality of memory cells (MC) along the height direction (Figs. 7-9).
Regarding claim 3, Jeong discloses the semiconductor device of claim 2, wherein
each of the plurality of memory cells (MC) includes
a first electrode (142) contacting one of the plurality of word lines (130-1),
a second electrode (156) contacting one of the plurality of bit lines (160-1), and
a switch memory (154) between the first electrode and the second electrode (Fig. 10).
Regarding claim 4, Jeong discloses the semiconductor device of claim 3, wherein
the first electrode (142), the switch memory (154), and the second electrode (146) overlap each other along the height direction (Fig. 10).
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Terada (US 10902913 B2).
Regarding claim 1, Terada discloses a semiconductor device comprising:
a plurality of word lines (RL) extending in a first direction (X, Fig. 3);
a plurality of bit lines (CL) extending in a second direction (Y) crossing the first direction;
a plurality of memory cells (MC) in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect; and
a semiconductor element (TR) connected (indirectly at least) to at least one of the plurality of word lines and the plurality of bit lines (Figs. 6, 8 and 10), the semiconductor element (TR; a transistor) including a first active pattern (gate of TR; shown in Figs. 6, 8 and 10) and a second active pattern (channel of TR; 6, 8 and 10) overlapping the first active pattern along a height direction (Z) perpendicular to the first and second directions (Figs. 6, 8 and 10).
Regarding claim 2, Terada discloses the semiconductor device of claim 1, wherein
the semiconductor element (TR) overlaps (partly at least) the plurality of memory cells (MC) along the height direction (Figs. 6, 8 and 10).
Allowable Subject Matter
Claims 7 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose or suggest (claim 7) wherein a width of the first active pattern is greater than a width of the second active pattern, (claim 12) a width of each of the plurality of first sheet patterns along a planar direction perpendicular to the height direction is greater than a width of each of the plurality of second sheet patterns along the planar direction perpendicular to the height direction, and (claim 13) wherein the semiconductor element includes a first source/drain area connected to the first active pattern, a second source/drain area connected to the second active pattern, and a gate structure crossing the first active pattern and the second active pattern; claims 14-20 depend from claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 8044456 B2 to Nagashima et al. discloses memory cells (MC) at intersection points of word lines (WLx) and bit lines (Blx, Fig. 2B) with a semiconductor element (at least 24) connected to a word line (Fig. 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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