Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on KR10-2023-0106422 filed on 08/14/2023.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 7, 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20230055499 A1 – hereinafter Lee).
Regarding Claim 1, Lee teaches a semiconductor device (see the entire document; Figs. 4 & 5; specifically, ([0039] - [0065]), and as cited below), comprising:
an upper conductive line (WL={WL1, WL2} – Fig. 4A – [0041]) extending in a first horizontal direction (into the page) over a substrate (100 – [0039]);
a channel layer (CP={VCP1, HCP, VCP2} – Fig. 5A – [0052]) facing the upper conductive line in a second horizontal direction (x-direction) that is perpendicular to the first horizontal direction (Fig. 4A);
a gate dielectric film ({Gox1, Gox2}) between the channel layer (CP) and the upper conductive line (WL);
a conductive contact pattern (LP – [0078] – Fig. 5A) comprising a lower surface (lower portion of LP), which is in contact with an upper surface of the channel layer (CP), and sidewalls including a first sidewall (inner sidewall), which faces the upper conductive line in the second horizontal direction (Fig. 5A shows lower portion of LP faces WL); and
an insulating spacer ({SP1, SP2} – [0065]) comprising a first portion (SP1 – Fig. 5A) between the upper conductive line (WL1 – as WL1 is part of WL) and the conductive contact pattern (right LP) in the second horizontal direction (Fig. 5A shows SP1 is between WL1 and right LP).
Regarding Claim 7, Lee teaches the semiconductor device of claim 1, further comprising a mold insulating pattern (125 – [0067]) arranged over the substrate (100) and defining a transistor region, wherein the channel layer (CP) comprises a vertical channel portion (VCP1, VCP2), which is in contact with the mold insulating pattern (125) and extends in a vertical direction in the transistor region (as shown in Fig. 5A), and the conductive contact pattern (LP) is in contact with the mold insulating pattern (125).
Regarding Claim 10, Lee teaches the semiconductor device of claim 1, wherein the channel layer comprises InGaZnO (IGZO), Sn-IGZO, InWO (IWO), InZnO (IZO), ZnSnO (ZTO), ZnO, yttrium-doped zinc oxide (YZO), InGaSiO (IGSO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, Si, Ge, SiGe, a Group III-V compound semiconductor, or a combination thereof (analogous channel 131 formed of IGZO – [0131]).
Regarding Claim 11, Lee teaches the semiconductor device of claim 1, wherein the insulating spacer comprises silicon oxide, silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof (analogous spacer 145 formed of Silicon nitride – [0145]).
Regarding Claim 12, Lee teaches the semiconductor device of claim 1, wherein the conductive contact pattern comprises Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, Ni, Ru, or a combination thereof (analogous LMP and UMP formed of titanium – [0110]).
Allowable Subject Matter
Claims 2-6, 8-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The semiconductor device of claim 1, wherein the sidewalls of the conductive contact pattern further comprise a second sidewall, which is on an opposite side to the first sidewall in the second horizontal direction, and the insulating spacer surrounds the sidewalls of the conductive contact pattern such that the insulating spacer is in contact with each of the first sidewall and the second sidewall of the conductive contact pattern.
Regarding claim 3: The semiconductor device of claim 1, wherein the sidewalls of the conductive contact pattern further comprise a second sidewall, which is on an opposite side to the first sidewall in the second horizontal direction, and the insulating spacer surrounds only some of the sidewalls of the conductive contact pattern such that the insulating spacer is in contact with the first sidewall of the conductive contact pattern and is not in contact with the second sidewall of the conductive contact pattern.
Regarding claim 4: The semiconductor device of claim 1, wherein the insulating spacer further comprises a second portion between the gate dielectric film and the conductive contact pattern.
Regarding claim 5: The semiconductor device of claim 1, wherein the conductive contact pattern further comprises a surface that is in contact with a sidewall of the channel layer.
Regarding claim 6: The semiconductor device of claim 1, further comprising a mold insulating pattern arranged over the substrate and defining a transistor region, wherein the channel layer comprises a vertical channel portion, which is in contact with the mold insulating pattern and extends in a vertical direction in the transistor region, and the conductive contact pattern is spaced apart from the mold insulating pattern in the second horizontal direction with the insulating spacer therebetween.
Regarding claim 8: The semiconductor device of claim 1, further comprising a mold insulating pattern arranged over the substrate and defining a transistor region, wherein a sidewall of the sidewalls of the conductive contact pattern, which faces the mold insulating pattern, comprises a curved surface that is convex toward the mold insulating pattern.
Regarding claim 9: The semiconductor device of claim 1, further comprising a mold insulating pattern arranged over the substrate and defining a transistor region, wherein the mold insulating pattern comprises a first mold insulating pattern and a second mold insulating pattern, which are sequentially stacked in a vertical direction and comprise different materials from each other, and the conductive contact pattern is in contact with each of the first mold insulating pattern and the second mold insulating pattern.
REASON FOR ALLOWANCE
Claims 13-20 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 13, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20230055499 A1 to Lee) substantially teach(es) some of limitations in claim 13 as indicated in the rejections of claim 1, but not the limitations of “each of the plurality of insulating spacers comprises a first portion between a corresponding upper conductive line of the plurality of upper conductive lines and a corresponding conductive contact pattern of the plurality of conductive contact patterns in the second horizontal direction” as recited in claim 13. Therefore, the claim 13 is deemed patentable over the prior art.
Regarding claims 14-17, they are allowed due to their dependencies on claim 13.
Regarding claim 18, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20230055499 A1 to Lee) substantially teach(es) some of limitations in claim 18 as indicated in the rejections of claim 1, but not the limitations of “a lower conductive line arranged on the peripheral circuit region and connected to the plurality of peripheral circuits” as recited in claim 18. Therefore, the claim 18 is deemed patentable over the prior art.
Regarding claims 19-20, they are allowed due to their dependencies on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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