Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2018/0151606).
Regarding claim 1, Park teaches a display device (Fig. 4-21, [0055-0212]), comprising:
a first sub-pixel, a second sub-pixel, and a third sub-pixel (three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]) disposed adjacent to each other (Fig. 4, [0056-0058]),
wherein each (Fig. 5-6, [0058]) of the first sub-pixel, the second sub-pixel, and the third sub-pixel (three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]) disposed adjacent to each other (Fig. 4, [0056-0058]) comprises:
a pixel circuit layer (Fig. 5-6) including a first transistor (Tdr in Fig. 5), a second transistor (Tsw1 in Fig. 5), and a third transistor (Tsw2 in Fig. 5) that are disposed on a substrate (Fig. 5-6 and 12),
a bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) disposed on a gate electrode (124b/124 in Fig. 6 and 12) of the first transistor (Tdr in Fig. 5-6 and 11) and a source electrode (111 in Fig. 6 and 12) of the second transistor (Tsw1 in Fig. 5-6 and 11), a first end of the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) is electrically connected (Fig. 5-6 and 11) to the source electrode (111 in Fig. 6 and 12) of the second transistor (Tsw1 in Fig. 5-6 and 11) and a second end of the bridge pattern is electrically connected (Fig. 5-6 and 11) to the gate electrode (124b/124 in Fig. 6 and 12) of the first transistor (Tdr in Fig. 5-6 and 11);
a first alignment electrode (131 in Fig. 6 and 12) and a second alignment electrode (133 in Fig. 6 and 12) disposed on the pixel circuit layer (Fig. 6 and 12) and spaced apart from each other (Fig. 6 and 12); and
light emitting elements (132 in Fig. 6 and 12) disposed on the first alignment electrode (131 in Fig. 6 and 12) and the second alignment electrode (133 in Fig. 6 and 12), and electrically connected to at least one of the first transistor, the second transistor, and the third transistor (Fig. 5-6 and 12),
wherein the second alignment electrode (133 in Fig. 6 and 12) is supplied with a low potential voltage ([0107], Fig. 5) and overlaps (Fig. 6 and 12, [0035, 0037, 0075, 0109, 0128]) the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) in a plan view (Fig. 6 and 12, [0035, 0037, 0075, 0108-0109, 0128], since Fig. 6 and 12 are cross-section view of a pixel, and 133 is vertically overlapping with 141 in Fig. 6 and 12, Park teaches that the second alignment electrode overlaps the bridge pattern in a plan view).
Regarding claims 2-4, Park also teaches the following elements:
(Claim 2) the pixel circuit layer (Fig. 6 and 12) includes a first insulating layer (103 in Fig. 6 and 12), a second insulating layer (104 in Fig. 6 and 12), a third insulating layer (105 in Fig. 6 and 12), a fourth insulating layer (106 in Fig. 6 and 12), and a fifth insulating layer (107 in Fig. 6 and 12) that are successively stacked on the substrate (Fig. 6 and 12), and wherein the source electrode (111 in Fig. 6 and 12) of the second transistor (Tsw1 in Fig. 5-6 and 11) is disposed on the first insulating layer (103 in Fig. 6 and 12), the gate electrode (124b/124 in Fig. 6 and 12) of the first transistor (Tdr in Fig. 5-6 and 11) is disposed on the second insulating layer (104 in Fig. 6 and 12), the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) is disposed on the third insulating layer (105 in Fig. 6), and the second alignment electrode (133 in Fig. 6 and 12) is disposed on the fifth insulating layer (107 in Fig. 6 and 12).
(Claim 3) the first end (the left end of 141 in Fig. 6 and 12) of the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) is electrically connected to the source electrode (111 in Fig. 6 and 12) of the second transistor through a first contact hole (the hole of 103, 104 and 105 above 111 in Fig. 6 and 12) formed through the second (104 in Fig. 6 and 12) and the third insulating layers (105 in Fig. 6 and 12), and wherein the second end (the right end of 141 in Fig. 6 and 12) of the bridge pattern is electrically connected to the gate electrode (124b/124 in Fig. 6 and 12) of the first transistor through a second contact hole (the hole of 105 above 124b/124 in Fig. 6 and 12) formed through the third insulating layer (105 in Fig. 6 and 12).
(Claim 4) the second alignment electrode (133 in Fig. 6 and 12) overlaps the first contact hole and the second contact hole (Fig. 6 and 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and in view of Lee (US 2022/0140036).
Regarding claim 12, Park teaches that the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) of the first sub-pixel (the first one of three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]), the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) of the third sub-pixel (the middle one of three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]), and the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) of the second sub-pixel (the last one of three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]) are arranged sequentially (Fig. 4, 6 and 12, [0058]) in a second direction (horizontal or vertical direction in Fig. 4) in a plan view (Fig. 4-6 and 12, [0035, 0037, 0075, 0108-0109, 0128]), wherein the second alignment electrode (133 in Fig. 6 and 12) overlaps (Fig. 6 and 12) the bridge pattern (132 in Fig. 6 and 12) of the first sub-pixel (the first one of three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]), the bridge pattern (132 in Fig. 6 and 12) of the third sub-pixel (the middle one of three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]), and the bridge pattern (132 in Fig. 6 and 12) of the second sub-pixel (the last one of three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]). Park does not teach the following elements.
Lee (US 2022/0140036) teaches the following elements (Fig. 2-3, [0099]):
(Claim 12) an second alignment electrode (270 in Fig. 3, [0099], the common electrode 270 may be disposed on the entire substrate) has a plate shape (Fig. 3, [0099]), extending in the second direction (Fig. 3, [0099]).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Lee (US 2022/0140036) for the system of Park such that in the system of Park,
(Claim 12) the second alignment electrode has a plate shape, extending in the second direction, and overlapping the bridge pattern of the first sub-pixel, the bridge pattern of the third sub-pixel, and the bridge pattern of the second sub-pixel.
The motivation is that parasitic capacitance is reduced and it helps to prevent luminance from being deteriorated (Lee (US 2022/0140036), [0143, 0007]).
Regarding claim 13, Park teaches that in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel (three adjacent 110 arranged in a horizontal or vertical direction in Fig. 4, [0056-0058]), the gate electrode (124b/124 in Fig. 6 and 12) of the first transistor (Tdr in Fig. 5-6 and 11), the source electrode (111 in Fig. 6 and 12) of the second transistor (Tsw1 in Fig. 5-6 and 11), and the bridge pattern (the pattern corresponding to 141 in Fig. 6 and 12) that are electrically connected to each other form a first node (the node corresponding to n2 in Fig. 5). Park does not teach the following elements.
Lee teaches the following elements (Fig. 1-3 and 12, [0099]):
(Claim 13) the second alignment electrode (270 in Fig. 3 and 12, [0099, 0143], the common electrode 270 may be disposed on the entire substrate) is disposed on the entire substrate ([0099]) and a shielding component to block parasitic capacitance occurring between nodes (Fig. 1, [0099]) the sub-pixels (PX1, PX2 and PX3 in Fig. 1) that are disposed adjacent to each other in the second direction (the vertical direction in Fig. 1).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Lee for the system of Park such that in the system of Park,
(Claim 13) the second alignment electrode is a shielding component to block parasitic capacitance occurring between the first nodes of the sub-pixels that are disposed adjacent to each other in the second direction.
The motivation is that parasitic capacitance is reduced and it helps to prevent luminance from being deteriorated (Lee, [0143, 0007]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and in view of Lee (US 2020/0226983).
Regarding claim 14, Park teaches that a data line (one of the data line DL in Fig. 4) configured to transmit a data signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel (three adjacent 110 arranged in a vertical direction in Fig. 4, [0056-0058]), and extending in a second direction (the vertical direction in Fig. 4). Park does not teach the following elements.
Lee (US 2020/0226983) teaches the following elements (Fig. 1 and 3, Table 1, [0052-0053, 0084, 0102, 0111, 0118]):
(Claim 14) a data line (Data/171 in Fig. 1, [0052-0053]) has a width of 8 μm (Table 1, [0118, 0052-0053, 0084, 0102, 0111]) in a first direction (the horizontal direction in Fig. 1 and 3) intersecting the second direction (the vertical direction in Fig. 1 and 3). It would have been obvious to one of ordinary skill in the art to recognize that the claimed range of approximately 7 μm is similar and close to the range disclosed by the prior art (MPEP 2144. 05 I.).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Lee (US 2020/0226983) for the system of Park to try and recognize that in the system of Park,
(Claim 14) the data line has a width of approximately 7 μm in a first direction intersecting the second direction.
The motivation is that an RC delay reduction effect may be effectively secured for a high resolution driving margin (Lee (US 2020/0226983), [0121]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and in view of Kim (US 2020/0312916).
Regarding claim 15, Park does not teach the following elements.
Kim teaches the following elements (Fig. 8-9, [0116-0122]):
(Claim 15) a first color conversion layer (CCPW in Fig. 9) disposed in a first sub-pixel (Pxa-W in Fig. 9), and a first color filter (W-CFP in Fig. 9) disposed on the first color conversion layer (Fig. 9); a second color conversion layer (CCP2 in Fig. 9) disposed in a second sub-pixel (Pxa-R in Fig. 9), and a second color filter (R-CFP in Fig. 9) disposed on the second color conversion layer (Fig. 9); and a third color conversion layer (CCP1 in Fig. 9) disposed in a third sub-pixel (Pxa-G in Fig. 9), and a third color filter (G-CFP in Fig. 9) disposed on the third color conversion layer (Fig. 9).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Kim for the system of Park to try and recognize that in the system of Park,
(Claim 15) a first color conversion layer disposed in the first sub-pixel, and a first color filter disposed on the first color conversion layer; a second color conversion layer disposed in the second sub-pixel, and a second color filter disposed on the second color conversion layer; and a third color conversion layer disposed in the third sub-pixel, and a third color filter disposed on the third color conversion layer.
The motivation is to generate a color image, color purity or color reproducibility may be improved, and a wide viewing angle may be improved. (Kim, [0003, 0066]).
Allowable Subject Matter
Claims 5-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record discloses or suggests all the combination of a display device as set forth in claims 5-11.
Regarding claim 5, none of the prior art discloses or suggests a display device recited in claim 3, wherein “the second alignment electrode overlaps the second contact hole and does not overlap the first contact hole” in combination with the other required elements of the claim.
Regarding claim 6, none of the prior art discloses or suggests a display device recited in claim 3, wherein “the second alignment electrode overlaps the first contact hole and does not overlap the second contact hole” in combination with the other required elements of the claim.
Regarding claims 7-11, none of the prior art discloses or suggests a display device recited in claim 2, wherein “each of the first sub-pixel, the second sub-pixel, and the third sub-pixel comprises: a contact electrode disposed on the third insulating layer; the fourth and the fifth insulating layers disposed on the contact electrode, and each including a contactor exposing the contact electrode; and electrodes disposed on the first alignment electrode, the second alignment electrode, and the light emitting elements on the fifth insulating layer, and electrically connected to the light emitting elements” in combination with the other required elements of the claim.
Claims 16-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 16, none of the prior art discloses or suggests that a display device, comprising: a substrate; a first sub-pixel, a third sub-pixel, and a second sub-pixel disposed adjacent to each other in a second direction, each including an emission area and a non-emission area, and disposed on the substrate; a first data line configured to apply a data signal to the first sub-pixel, a second data line configured to apply a data signal to the second sub-pixel, and a third data line configured to apply a data signal to the third sub-pixel; light emitting elements disposed in the respective emission areas of the first sub-pixel, the second sub-pixel and the third sub-pixel; a first transistor, a second transistor, and a third transistor positioned between the substrate and the light emitting elements, and electrically connected to the light emitting elements; a bridge pattern electrically connecting a gate electrode of the first transistor and a source electrode of the second transistor; wherein “a first alignment electrode and a second alignment electrode positioned between the bridge pattern and the light emitting elements, and disposed to be spaced apart from each other; and electrodes disposed on the first alignment electrode and the second alignment electrode, and electrically connected to the light emitting elements, wherein the second alignment electrode overlaps the bridge pattern of the first sub-pixel, the bridge pattern of the second sub-pixel, and the bridge pattern of the third sub-pixel in a plan view” in combination with the other required elements of the claim.
The most relevant reference, the prior art to Park (US 2018/0151606), Lee (US 2022/0140036), Lee (US 2020/0226983) and Kim (US 2020/0312916), taken along or in combination, only discloses a display device, comprising: a substrate; a first sub-pixel, a third sub-pixel, and a second sub-pixel disposed adjacent to each other in a second direction, each including an emission area and a non-emission area, and disposed on the substrate; a first data line configured to apply a data signal to the first sub-pixel, a second data line configured to apply a data signal to the second sub-pixel, and a third data line configured to apply a data signal to the third sub-pixel; light emitting elements disposed in the respective emission areas of the first sub-pixel, the second sub-pixel and the third sub-pixel; a first transistor, a second transistor, and a third transistor positioned between the substrate and the light emitting elements, and electrically connected to the light emitting elements; a bridge pattern electrically connecting a gate electrode of the first transistor and a source electrode of the second transistor; a first alignment electrode and a second alignment electrode, wherein the second alignment electrode overlaps the bridge pattern of the first sub-pixel, the bridge pattern of the second sub-pixel, and the bridge pattern of the third sub-pixel in a plan view. However they do not teach or suggest the combined limitations of “a first alignment electrode and a second alignment electrode positioned between the bridge pattern and the light emitting elements, and disposed to be spaced apart from each other; and electrodes disposed on the first alignment electrode and the second alignment electrode, and electrically connected to the light emitting elements, wherein the second alignment electrode overlaps the bridge pattern of the first sub-pixel, the bridge pattern of the second sub-pixel, and the bridge pattern of the third sub-pixel in a plan view” in combination with the other required elements of the claim.
Dependent 17-20 would be allowable by virtue of their dependency.
Conclusion
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/Shan Liu/
Primary Examiner, Art Unit 2871
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