DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-9, 12, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Patent Application Publication Number 2024/0110976) and Xia et al. (U.S. Patent Application Publication Number 2011/0078525).
Regarding Claim 1, Huang discloses a system (Figure 1, item 10) comprising:
control circuitry (Figure 1, item CCG3, paragraph 0015) configured to:
enable a first clock signal (Figure 1, item CLKS3) to drive an active device-under-test (Figure 1, item 100, paragraph 0017; i.e., the device under test 100 is “active” in that it is receiving the first clock signal to so that it can be tested) among multiple devices (Figure 1, items 100 and 140) coupled to a power supply (paragraph 0014; i.e., the circuit 10 is powered on, which would indicate a power supply is present), wherein the first clock signal comprises:
a first portion that includes a first set of clock cycles;
a second portion that includes a second set of clock cycles;
a third portion that includes a third set of clock cycles;
a first idle portion between the first portion and the second portion; and
a second idle portion between the second portion and the third portion (paragraphs 0017 and 0020; i.e., the first clock signal CLKS3 may be enabled and disabled based on whether the test signal TEDUT is at a high or low value; therefore, the first clock signal CLKS3 may contain a first, second, and third set of clock cycles [periods in which the test signal TEDUT is a high level], in which there are first and second idle portions between those sets of clock cycles [periods in which the test signal TEDUT is a low level]); and
during the first and second idle portions, enable a second clock signal supplied to one or more inactive devices (paragraphs 0007 and 0019; i.e., in the power saving mode, the function circuit 140 is stopped/inactive) among the multiple devices (Figure 1, item 140, paragraphs 0017, 0020, and 0030; i.e., the second clock signal CLKP3 is separately controlled by the enable signal EN3; this enable signal EN3 is placed at a high or low value depending on whether the system 10 is in a power saving state which is independent of the test mode signal TEDUT; therefore, the test mode TEDUT may be off [at a low level] in which the first clock signal CLKS3 is idle, while the power saving state is turned off [and the function circuit 140 is stopped/inactive] in which the second clock signal CLKP3 is enabled [the ENP signal within item CCG3 is at a high level]; this would result in the second clock signal CLKP3 being enabled during the first and second idle portions of the first clock signal CLKS3).
Huang does not expressly disclose wherein the multiple devices are each devices-under-test; and
wherein the multiple devices-under-test are each coupled to the power supply.
In the same field of endeavor (e.g., clock control techniques for a device under test), Xia teaches wherein the multiple devices are each devices-under-test (Figure 1, items 41-44); and
wherein the multiple devices-under-test are each coupled to the power supply (Figure 1, item 60, claims 18 and 20; i.e., the ATE scan test unit provides power as well as clock signals for the multiple DUTs 41-44 to be tested).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Xia’s teachings of clock control techniques for a device under test with the teachings of Huang, for the purpose of avoiding the need to have two separate power supplies in the system, thereby reducing costs.
Regarding Claim 3, Huang discloses the multiple devices-under-test, the active device-under-test configured to perform a scan-chain test during a scan cycle based on the first clock signal (paragraph 0021; i.e., a scan mode may be entered for the device under test).
Regarding Claim 6, Huang discloses wherein the second clock signal comprises a first portion that includes a fourth set of clock cycles and a second portion having a fifth set of clock cycles (paragraphs 0017 and 0020; i.e., the power saving mode may be enabled and disabled at different times; this would result in the second clock signal CLKP3 having two separate portions in which there would be the claimed “fourth set of clock cycles” and “fifth set of clock cycles”).
Regarding Claim 7, Huang discloses wherein the first set of clock cycles and the third set of clock cycles include the same number of clock cycles (paragraphs 0017 and 0020; i.e., depending on how long the user or designer chooses to enable the test mode and power savings mode, the first and third sets of clock cycles may include the same number of clock cycles [e.g., if the time duration of the test mode and power savings mode was the same]).
Regarding Claim 8, Huang discloses wherein the number of clock cycles of the fourth and fifth sets of clock cycles is based on a duration of the first and second idle portions, respectively (paragraphs 0017 and 0020; i.e., if the user chooses to enable the test mode only while the remaining parts of the circuit are in the power savings mode, then the fourth and fifth sets of clock cycles [in which the power saving mode is turned off] would be based on the specific durations of the first and second idle portions [in which the test mode is turned off]).
Regarding Claim 9, Huang discloses wherein the control circuitry is further configured to identify a first frequency of the first clock signal (paragraph 0013; i.e., the first clock signal CLKS3 is based on the frequency of the system clock CLK [the claimed “first frequency”]); and during the first and second idle portions, enable the second clock signal at a second frequency based on the first frequency (paragraph 0013; i.e., the frequency of the second clock signal CLKP3 is also based on the frequency of the system clock CLK [see initial branch-off of system CLK to function circuit 110- the reference does not state that the frequencies are ever changed]).
Regarding Claim 12, Huang discloses a device (Figure 1, item 10) comprising:
a circuit (Figure 1, item CCG3, paragraph 0015) to:
enable a first clock signal (Figure 1, item CLKS3) to drive an active device-under-test (Figure 1, item 100, paragraph 0017; i.e., the device under test 100 is “active” in that it is receiving the first clock signal to so that it can be tested) among multiple devices (Figure 1, items 100 and 140) coupled to a power supply (paragraph 0014; i.e., the circuit 10 is powered on, which would indicate a power supply is present), wherein the first clock signal comprises:
a first portion that includes a first set of clock cycles;
a second portion that includes a second set of clock cycles;
a third portion that includes a third set of clock cycles;
a first idle portion between the first portion and the second portion; and
a second idle portion between the second portion and the third portion (paragraphs 0017 and 0020; i.e., the first clock signal CLKS3 may be enabled and disabled based on whether the test signal TEDUT is at a high or low value; therefore, the first clock signal CLKS3 may contain a first, second, and third set of clock cycles [periods in which the test signal TEDUT is a high level], in which there are first and second idle portions between those sets of clock cycles [periods in which the test signal TEDUT is a low level]); and
during the first and second idle portions, enable a second clock signal supplied to one or more inactive devices (paragraphs 0007 and 0019; i.e., in the power saving mode, the function circuit 140 is stopped/inactive) among the multiple devices (Figure 1, item 140, paragraphs 0017, 0020, and 0030; i.e., the second clock signal CLKP3 is separately controlled by the enable signal EN3; this enable signal EN3 is placed at a high or low value depending on whether the system 10 is in a power saving state which is independent of the test mode signal TEDUT; therefore, the test mode TEDUT may be off [at a low level] in which the first clock signal CLKS3 is idle, while the power saving state is turned off [and the function circuit 140 is stopped/inactive] in which the second clock signal CLKP3 is enabled [the ENP signal within item CCG3 is at a high level]; this would result in the second clock signal CLKP3 being enabled during the first and second idle portions of the first clock signal CLKS3).
Huang does not expressly disclose wherein the circuit is a processor coupled with one or more computer readable storage media; and
program instructions stored on the one or more computer readable storage media that, when executed, direct the processor to perform the claimed steps;
wherein the multiple devices are each devices-under-test; and
wherein the multiple devices-under-test are each coupled to the power supply.
In the same field of endeavor, Xia teaches wherein the circuit is a processor coupled with one or more computer readable storage media (claim 19); and
program instructions stored on the one or more computer readable storage media that, when executed, direct the processor to perform a series of steps (claim 19);
wherein the multiple devices are each devices-under-test (Figure 1, items 41-44); and
wherein the multiple devices-under-test are each coupled to the power supply (Figure 1, item 60, claims 18 and 20; i.e., the ATE scan test unit provides power as well as clock signals for the multiple DUTs 41-44 to be tested).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 12.
Regarding Claim 15, Huang discloses wherein the second clock signal comprises a first portion that includes a fourth set of clock cycles and a second portion having a fifth set of clock cycles (paragraphs 0017 and 0020; i.e., the power saving mode may be enabled and disabled at different times; this would result in the second clock signal CLKP3 having two separate portions in which there would be the claimed “fourth set of clock cycles” and “fifth set of clock cycles”); the number of clock cycles of the fourth and fifth sets of clock cycles is based on a duration of the first and second idle portions, respectively (paragraphs 0017 and 0020; i.e., if the user chooses to enable the test mode only while the remaining parts of the circuit are in the power savings mode, then the fourth and fifth sets of clock cycles [in which the power saving mode is turned off] would be based on the specific durations of the first and second idle portions [in which the test mode is turned off]).
Regarding Claim 16, Huang discloses wherein a frequency of the second clock signal is based on one or more of (paragraph 0013; i.e., the frequency of the second clock signal CLKP3 is also based on the frequency of the system clock CLK [see initial branch-off of system CLK to function circuit 110]): a frequency of the first clock signal (paragraph 0013; i.e., the first clock signal CLKS3 is based on the frequency of the system clock CLK [the claimed “first frequency”]), an amount of voltage received from the power supply at the active device-under-test while the active device-under-test is driven by the first clock signal, and an impedance of the active device-under-test.
Regarding Claim 17, Huang discloses a system (Figure 1, item 10) comprising:
a first clock terminal (Figure 1, item GCKS, paragraph 0016);
a second clock terminal (Figure 1, item GCKP, paragraph 0016); and
control circuitry (Figure 1, item CCG3, paragraph 0015) coupled to the first clock terminal and the second clock terminal, wherein the control circuitry is configured to:
enable, via the first clock terminal, a first clock signal (Figure 1, item CLKS3) to drive an active device-under-test (Figure 1, item 100, paragraph 0017; i.e., the device under test 100 is “active” in that it is receiving the first clock signal to so that it can be tested) among multiple devices (Figure 1, items 100 and 140) coupled to a power supply (paragraph 0014; i.e., the circuit 10 is powered on, which would indicate a power supply is present), wherein the first clock signal comprises:
a first portion that includes a first set of clock cycles;
a second portion that includes a second set of clock cycles;
a third portion that includes a third set of clock cycles;
a first idle portion between the first portion and the second portion; and
a second idle portion between the second portion and the third portion (paragraphs 0017 and 0020; i.e., the first clock signal CLKS3 may be enabled and disabled based on whether the test signal TEDUT is at a high or low value; therefore, the first clock signal CLKS3 may contain a first, second, and third set of clock cycles [periods in which the test signal TEDUT is a high level], in which there are first and second idle portions between those sets of clock cycles [periods in which the test signal TEDUT is a low level]); and
during the first and second idle portions, enable, via the second clock terminal, a second clock signal supplied to one or more inactive devices (paragraphs 0007 and 0019; i.e., in the power saving mode, the function circuit 140 is stopped/inactive) among the multiple devices (Figure 1, item 140, paragraphs 0017, 0020, and 0030; i.e., the second clock signal CLKP3 is separately controlled by the enable signal EN3; this enable signal EN3 is placed at a high or low value depending on whether the system 10 is in a power saving state which is independent of the test mode signal TEDUT; therefore, the test mode TEDUT may be off [at a low level] in which the first clock signal CLKS3 is idle, while the power saving state is turned off [and the function circuit 140 is stopped/inactive] in which the second clock signal CLKP3 is enabled [the ENP signal within item CCG3 is at a high level]; this would result in the second clock signal CLKP3 being enabled during the first and second idle portions of the first clock signal CLKS3).
Huang does not expressly disclose wherein the multiple devices are each devices-under-test; and
wherein the multiple devices-under-test are each coupled to the power supply.
In the same field of endeavor, Xia teaches wherein the multiple devices are each devices-under-test (Figure 1, items 41-44); and
wherein the multiple devices-under-test are each coupled to the power supply (Figure 1, item 60, claims 18 and 20; i.e., the ATE scan test unit provides power as well as clock signals for the multiple DUTs 41-44 to be tested).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 17.
Claims 2, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Huang and Xia as applied to claims 1, 12, and 17 above, and further in view of Arsovski et al. (U.S. Patent Application Publication Number 2008/0046772).
Regarding Claims 2, 13, and 18, Huang and Xia do not expressly disclose wherein the first and second idle portions create noise in the power supply coupled to the multiple devices-under-test; and the second clock signal offsets the noise in the power supply.
In the same field of endeavor (e.g., clocking techniques), Arsovski teaches wherein the first and second idle portions create noise in the power supply coupled to a multiple devices-under-test (paragraph 0002; i.e., the combination of Arsovski with Huang and Xia would contain a power supply coupled to multiple devices-under-test); and the second clock signal offsets the noise in the power supply (Figure 3, items 20, paragraphs 0015-0016; i.e., a second clock signal may offset/reduce the power supply noise by being active/at a high level when a first clock is inactive/at a low level).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Arsovski’s teachings of clocking techniques with the teachings of Huang and Xia, for the purpose of reducing the noise in the system, thereby preventing data loss during the clock transitions.
Claims 4, 5, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang and Xia as applied to claims 3, 12, and 17 above, and further in view of Srinivasan et al. (U.S. Patent Application Publication Number 2015/0198665).
Regarding Claims 4 and 19, Huang and Xia do not expressly disclose wherein the scan cycle comprises a scan-in portion, a functional capture portion, and a scan-out portion, and wherein the first portion of the first clock signal corresponds to the scan-in portion, the second portion of the first clock signal corresponds to the functional capture portion, and the third portion of the first clock signal corresponds to a scan-out portion.
In the same field of endeavor (e.g., circuit testing), Srinivasan teaches wherein the scan cycle comprises a scan-in portion, a functional capture portion, and a scan-out portion (paragraph 0019), and wherein the first portion of the first clock signal corresponds to the scan-in portion, the second portion of the first clock signal corresponds to the functional capture portion, and the third portion of the first clock signal corresponds to a scan-out portion (paragraphs 0020 and 0028; i.e., since only a single clock 105 is used to perform each of the scan functions one at a time, each of the scan-in, functional capture, and scan-out portions must occur in three different portions of the clock signal 105).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Srinivasan’s teachings of circuit testing with the teachings of Huang and Xia, for the purpose of improving the controllability and observability of internal circuit nodes, which makes testing and diagnosing manufacturing defects more efficient and cost-effective (a known benefit of scan-chain testing).
Regarding Claim 5, Huang discloses wherein the control circuitry is configured to, in response to detecting an end of the scan-in portion, enable the second clock signal (paragraph 0021; i.e., Huang discloses a scan mode, which would include a start and end to a scan-in portion; Huang further discloses that the test mode can be discontinued and a second clock signal can be transmitted to another circuit; therefore, the second clock could be transmitted to the other circuit in response to detecting an end of the scan-in portion).
Regarding Claim 14, Huang and Xia disclose the program instructions direct the processor (Xia, claim 19) to enable the second clock signal in response to detecting an end of the scan-in portion (Huang, paragraph 0021; i.e., Huang discloses a scan mode, which would include a start and end to a scan-in portion; Huang further discloses that the test mode can be discontinued and a second clock signal can be transmitted to another circuit; therefore, the second clock could be transmitted to the other circuit in response to detecting an end of the scan-in portion).
Huang and Xia do not expressly disclose the active device-under-test is configured to perform a scan-chain test during a scan cycle based on the first clock signal; the scan cycle comprises a scan-in portion, a functional capture portion, and a scan-out portion, and wherein the first portion of the first clock signal corresponds to the scan-in portion, the second portion of the first clock signal corresponds to the functional capture portion, and the third portion of the first clock signal corresponds to a scan-out portion.
In the same field of endeavor, Srinivasan teaches the active device-under-test is configured to perform a scan-chain test during a scan cycle based on the first clock signal; the scan cycle comprises a scan-in portion, a functional capture portion, and a scan-out portion (paragraph 0019), and wherein the first portion of the first clock signal corresponds to the scan-in portion, the second portion of the first clock signal corresponds to the functional capture portion, and the third portion of the first clock signal corresponds to a scan-out portion (paragraphs 0020 and 0028; i.e., since only a single clock 105 is used to perform each of the scan functions one at a time, each of the scan-in, functional capture, and scan-out portions must occur in three different portions of the clock signal 105).
The motivation discussed above with regards to Claim 4 applies equally as well to Claim 14.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and Xia as applied to claim 7 above, and further in view of Tanaka et al. (U.S. Patent Application Publication Number 2009/0058452).
Regarding Claim 10, Huang and Xia do not expressly disclose wherein the control circuitry is further configured to identify an amount of voltage received from the power supply at the active device-under-test while the active device-under-test is driven by the first clock signal; and during the first and second idle portions, enable the second clock signal at a frequency based on the amount of voltage.
In the same field of endeavor (e.g., device testing techniques), Tanaka teaches wherein the control circuitry is further configured to identify an amount of voltage (Figure 1, item Vdd, paragraph 0020) received from the power supply (Figure 1, item 13) at the active device-under-test (Figure 1, item 1) while the active device-under-test is driven by the first clock signal (Figure 1, item 21, paragraph 0023); and during the first and second idle portions, enable the second clock signal (paragraph 0030; i.e., there may be two separate clock signals- one that is provided when the test signal is enabled [the “first clock signal”] and one when it is not enabled [the “second clock signal”- this is when the first clock signal is in its idle portions]) at a frequency based on the amount of voltage (paragraph 0027; i.e., the generated second clock signal is based on the amount of voltage Vdd supplied to the DUT 1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Tanaka’s teachings of device testing techniques with the teachings of Huang and Xia, for the purpose of being able to test how much the DUT is affected by power supply variations, which would allow a designer to know the allowable range that a power supply can provide a voltage before the device fails.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang and Xia as applied to claims 1 and 17 above, and further in view of Kapur (U.S. Patent Application Publication Number 2006/0091928).
Regarding Claims 11 and 20, Huang and Xia do not expressly disclose wherein the control circuitry is further configured to, during the first and second idle portions, enable a third clock signal supplied to the one or more inactive devices-under-test, wherein the third clock signal comprises a phase-shifted set of clock cycles 180-degrees-out-of-phase relative to the first clock signal and the second clock signal.
In the same field of endeavor (e.g., device testing techniques), Kapur teaches wherein the control circuitry is further configured to, during the first and second idle portions (Figure 2; i.e., see multiple low levels/idle portions of clocks C and C0), enable a third clock signal (Figure 2, item C180) supplied to the one or more inactive devices-under-test (paragraph 0044), wherein the third clock signal comprises a phase-shifted set of clock cycles 180-degrees-out-of-phase relative to the first clock signal and the second clock signal (paragraph 0023; i.e., the third clock signal C180 is enabled while the first clock signal C and second clock signal C0 are at their idle levels and is 180 degrees out of phase relative to both C and C0, which are in-phase with one another).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kapur’s teachings of device testing techniques with the teachings of Huang and Xia, for the purpose of helping to provide multiple clocks in a glitch-free manner (see Kapur, paragraph 0006). Providing multiple clocks that are out of phase with respect to one another has the known benefit of allowing the system to better manage data paths with varying delays (imbalanced paths). This relaxation of path balancing requirements means fewer flip-flops (DFFs) are needed to synchronize data between different parts of the circuit, which in turn reduces the overall circuit area.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system that enables clock signals for a device under test.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175