DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 05/31/2024.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/03/2025 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0338207 A1 (Chen) and further in view of US 2018/0033771 A1 (Yu).
Regarding claim 1, Chen discloses, a package comprising:
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a substrate (501; carrier substrate; Fig. 6; [0044]); and a passive device (103; integrated passive device (IPD); Fig. 4; [0023]) coupled to the substrate (501),
the passive device (103) comprising:
a trench capacitor device (deep-trench capacitors are part of IPD 103; [0024]);
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But Chen fails to teach explicitly, passive devices coupled to the substrate through a first plurality of solder interconnects; an encapsulation layer; and a metallization portion coupled to the trench capacitor device and the encapsulation layer.
However, in analogous art, Yu discloses, passive devices (170; IPD components; Fig. 20A; [0047]) coupled (through via 112; Fig. 8; [0028]) to the substrate (100) through a first plurality of solder interconnects (176; micro bump; Fig. 20A; [0047]);
an encapsulation layer (156; dielectric layer, part of IPD 170; Fig. 20A; [0045]); and
a metallization portion (as annotated on Fig. 20A; [0027], [0048]) coupled to the trench capacitor device (part of IPD 170) and the encapsulation layer (156).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Yu before him/her, to modify the teachings of a package with passive device as taught by Chen and to include the teachings of solder interconnects, encapsulation layer and metallization layer as taught by Yu since these components are usually part of a package structure and absent these important teachings in Chen, a person with ordinary skill in the art would be motivated to reach out to Yu while forming a package of Chen.
Regarding claim 2, the combination of Chen and Yu discloses, the package of claim 1, wherein the metallization portion (as annotated on Fig. 20A; [0027]) comprises: at least one dielectric layer (132/140; dielectric layers; Fig. 12; [0027]); and a plurality of metallization interconnects (138/146; metallization patterns; Fig. 12; [0027]; Yu Reference).
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Regarding claim 3, the combination of Chen and Yu discloses, the package of claim 2, wherein the plurality of metallization interconnects (138/146; metallization patterns; Fig. 12; [0027]) comprise at least one bar metallization interconnect (both 138 and 146 are partially bar pattern; Fig. 12; Yu Reference).
Regarding claim 4, the combination of Chen and Yu discloses, the package of claim 2, wherein the plurality of metallization interconnects 138/146; metallization patterns; Fig. 12; [0027]) comprises a plurality of bar metallization interconnects (both 138 and 146 are partially bar pattern; Fig. 12) but fails to teach explicitly, the plurality of bar metallization interconnects located along a periphery of the trench capacitor device.
However, in MPEP 2144.04 (VI) (C), it is stated that Rearrangement of Parts is held to be an obvious matter of design choice, if it does not modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). With this teaching, the plurality of bar metallization interconnects could be located along the periphery of the trench capacitor device. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0033] – [0035] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Regarding claim 5, the combination of Chen and Yu fails to teach explicitly, the package of claim 4, wherein the plurality of bar metallization interconnects are configured to provide an electrical path for ground.
However, the above limitation ‘wherein the plurality of bar metallization interconnects are configured to provide an electrical path for ground’ is a ‘functional description’ of bar metallization interconnects. This functional description does not define additional structural aspects of the claimed invention. The package of Yu is capable of performing the function. Thus, the examiner notes that since claims are the disclosure of applicant’s invention for which protection is sought, therefore, ‘wherein the plurality of bar metallization interconnects are configured to provide an electrical path for ground’ is considered taught by the combination of Chen and Yu. See MPEP 2114 (I). In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432. See also Bettcher Industries, Inc. v. Bunzl USA, Inc., 661 F.3d 629, 639-40,100 USPQ2d 1433, 1440 (Fed. Cir. 2011).
Regarding claim 6, the combination of Chen and Yu discloses, the package of claim 2, wherein the first plurality of solder interconnects (176) are coupled to the plurality of metallization interconnects (138/146; metallization patterns; Fig. 12; [0027]; Yu Reference).
Regarding claim 7, the combination of Chen and Yu discloses, the package of claim 2, wherein the passive device (170; IPD components; Fig. 20A; [0047]) is coupled (through via 112; Fig. 8; [0028]) to a first surface (top surface; Fig. 20A) of the substrate (100) through the first plurality of solder interconnects (176, as annotated on Fig. 20A; Fig. 20A; [0047]; Yu Reference).
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Regarding claim 8, the combination of Chen and Yu discloses, the package of claim 7, further comprising a second plurality of solder interconnects (176, as annotated on Fig. 20A) coupled (through via 112; Fig. 8; [0028]) to the first surface (top surface; Fig. 20A) of the substrate (100) (Fig. 20A; Yu Reference).
Regarding claim 10, Chen discloses, the package of claim 8, further comprising an integrated device (1407; third semiconductor device; Fig. 15; [0106]) coupled to a second surface (top surface) of the substrate (as annotated on Fig. 15) through a third plurality of solder interconnects (as annotated on Fig. 15).
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Regarding claim 13, Chen discloses, the package of claim 1, wherein the trench capacitor device (103) comprises: a die substrate (101; first substrate; Fig. 4; [0023]); and
a plurality of trench capacitors (individual 103s) located at least partially in the die substrate (101).
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Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0338207 A1 (Chen) and further in view of US 2018/0033771 A1 (Yu).
Regarding claim 1, Chen discloses, the passive device (103, IPD) comprising:
a trench capacitor device (deep-trench capacitors are part of IPD 103; [0024]);
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But Chen fails to teach explicitly, the passive device comprising an encapsulation layer; and a metallization portion coupled to the trench capacitor device and the encapsulation layer.
However, in analogous art, Yu discloses, passive devices (170; IPD components; Fig. 20A; [0047]) comprising an encapsulation layer (156; dielectric layer, part of IPD 170; Fig. 20A; [0045]); and
a metallization portion (as annotated on Fig. 20A; [0027], [0048]) coupled to the trench capacitor device (part of IPD 170) and the encapsulation layer (156).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Yu before him/her, to modify the teachings of a package with passive device as taught by Chen and to include the teachings of encapsulation and metallization layers in passive device as taught by Yu since these components are usually part of a package structure and absent these important teachings in Chen, a person with ordinary skill in the art would be motivated to reach out to Yu while forming a package of Chen.
Regarding claim 15, the combination of Chen and Yu discloses, the passive device of claim 14, wherein the metallization portion (as annotated on Fig. 20A; [0027]) comprises: at least one dielectric layer (132/140; dielectric layers; Fig. 12; [0027]); and a plurality of metallization interconnects (138/146; metallization patterns; Fig. 12; [0027]; Yu Reference).
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Regarding claim 16, the combination of Chen and Yu discloses, the passive device of claim 15, wherein the plurality of metallization interconnects (138/146; metallization patterns; Fig. 12; [0027]) comprise at least one bar metallization interconnect (both 138 and 146 are partially bar pattern; Fig. 12; Yu Reference).
Regarding claim 17, the combination of Chen and Yu discloses, the passive device of claim 15, wherein the plurality of metallization interconnects 138/146; metallization patterns; Fig. 12; [0027]) comprises a plurality of bar metallization interconnects (both 138 and 146 are partially bar pattern; Fig. 12) but fails to teach explicitly, the plurality of bar metallization interconnects located along a periphery of the trench capacitor device.
However, in MPEP 2144.04 (VI) (C), it is stated that Rearrangement of Parts is held to be an obvious matter of design choice, if it does not modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). With this teaching, the plurality of bar metallization interconnects could be located along the periphery of the trench capacitor device. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0033] – [0035] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Regarding claim 18, Chen discloses, the passive device of claim 14, wherein the trench capacitor device (103) comprises: a die substrate (101; first substrate; Fig. 4; [0023]); and
a plurality of trench capacitors (individual 103s) located at least partially in the die substrate (101).
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Regarding claim 19, the combination of Chen and Yu discloses, the passive device of claim 18, wherein the encapsulation layer (156; dielectric layer, part of IPD 170; Fig. 20A; [0045]; Yu Ref.) is coupled to the die substrate (101; Chen Ref.) and the metallization portion (as annotated on Fig. 20A; [0027], [0048]; Yu Ref.).
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Regarding claim 20, the combination of Chen and Yu discloses, the passive device of claim 14, wherein the metallization portion (as annotated on Fig. 20A; [0027], [0048]; Yu Ref.) is coupled to a front side of the trench capacitor device (combining Chen and Yu would make the metallization portion to couple to the front side of the trench capacitor device.
Allowable Subject Matter
Claims 9 and 11-12 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 9, the closest prior art, US 2017/0338207 A1 (Chen), in conjunction with US 2018/0033771 A1 (Yu), and in combination with the other claimed features, fails to disclose, “the package of claim 8, wherein a region between an edge of the passive device and a nearest solder interconnect from the plurality of solder interconnects has a minimum spacing of about 280 micrometers”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the package of claim 8, wherein a region between an edge of the passive device and a nearest solder interconnect from the plurality of solder interconnects has a minimum spacing of about 280 micrometers,’ is material to the inventive concept of the application at hand to provide a package including a passive device which can be placed closer to nearby solder balls, thereby reducing package footprint while maintaining reliability.
Regarding claim 11, the closest prior art, US 2017/0338207 A1 (Chen), in conjunction with US 2018/0033771 A1 (Yu), and in combination with the other claimed features, fails to disclose, “the package of claim 10, further comprising an underfill located between the integrated device and the first surface of the substrate”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the package of claim 10, further comprising an underfill located between the integrated device and the first surface of the substrate,’ is material to the inventive concept of the application at hand to provide a package including a passive device which can be placed closer to nearby solder balls, thereby reducing package footprint while maintaining reliability.
Claim 12 is also objected to due to its dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0223585 A1 (Kim) - A capacitor assembly is disclosed including a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.
US 2022/0189919 A1 (Jeng) – A semiconductor structure including a first semiconductor device and a second semiconductor device is disclosed. A first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.
US 2021/0098567 A1 (Kim) - A package is disclosed including a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
06/12/2026
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