DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1-5, 8-9, 11-13 and 17-20 have been amended.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 03/30/2026 with respect to Claim(s) 1-20 have been fully considered but they are not persuasive.
Applicant's arguments with respect to Claim(s) 1-20 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-20 herein.
Claim Objections
Claim(s) 2-3, 11-12 and 17 are objected to because of the following informalities:
Claim 2 recites a phrase “measuring resistance of multiple nominally identical integrated circuit resistors” in line 3. Examiner suggests amending the phrase to recite “measuring resistances of multiple nominally identical integrated circuit resistors” to restore clarity.
Claim 3 recites a phrase “measuring capacitance of multiple nominally identical capacitors” in line 3. Examiner suggests amending the phrase to recite “measuring capacitances of multiple nominally identical capacitors” to restore clarity.
Claim 11 recites a phrase “ratios including a resistance of the multiple nominally identical integrated circuit resistors and a resistance of the reference integrated circuit resistor” in last paragraph. Examiner suggests amending the phrase to recite “ratios including resistances of the multiple nominally identical integrated circuit resistors to a resistance of the reference integrated circuit resistor” to restore clarity.
Claim 12 recites a phrase “ratios including a capacitance of the multiple nominally identical integrated circuit capacitors and a capacitance of the reference capacitor resistor” in last paragraph. Examiner suggests amending the phrase to recite “ratios including capacitances of the multiple nominally identical integrated circuit capacitors to a capacitance of the reference capacitor” to restore clarity.
Claim 17 recites a phrase “of interest of interest” in line 8. Examiner suggests amending the phrase to recite “of interest” to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7-11, 13, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Devadas et al. (US 20030204743; hereinafter Devadas) in view of Burns et al. (US 7843205).
Regarding claim 1, Devadas teaches in figure(s) 1-56 a method comprising:
measuring (measurement circuit 104; fig. 1) a circuit parameter (measurable component 102) of multiple integrated circuit elements of an integrated circuit chip (50) of interest to produce an individualized identifier (para. 3 - uniquely identified by embedding a unique identifier in the chip, such as a serial number embedded in the chip by the manufacturer… generating a unique identifier is to incorporate an array of transistors in the chip, measure the threshold voltages of the transistors in the array, and output the measurements as the identifier… no two chips will have arrays of transistors whose threshold voltages are exactly the same) for the integrated circuit chip of interest using multiple measurements of the circuit parameter;
comparing the individualized identifier to an identifier database including identifiers of multiple integrated circuit chips (277 in fig. 2; para. 6 - authenticate the chip by selectively measuring a subset of the physical characteristics and comparing the measured results with pre-stored measurements; para. 26 - a storage device to store identifiers and responses associated with the device, each identifier identifying one or more measurable characteristics, each response corresponding to one or more identifiers and is derived from one or more measurements of the measurable characteristics identified by the one or more identifiers); and
identifying the integrated circuit chip of interest as a specific integrated circuit chip of the identifier database using the comparing of the individualized identifier to the identifier database (output in figs. 9-11,14; para. 57 - PUF circuit 100 receives an input on a signal line 106 and generates an output on line 108. Each (input, output) pair is specific to chip 50 and depends on characteristics of a portion of the physical structure associated with chip 50… the (input, output) pairs can be used to authenticate and identify chip 50 or to prove that the message is generated by a particular chip).
Devadas does not teach explicitly wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements.
However, Burns teaches in figure(s) 1-10 wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements (col. 1 lines 25-28 :- IC integrated circuits may be characterized in terms of various circuit parameters, such as sheet-rho; clms. 11,16 - measure of a first manufacturing process-dependent circuit parameter …wherein the first manufacturing process-dependent circuit parameter is a sheet resistance of a resistor disposed on the integrated circuit chip; figs. 1-3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements as taught by Burns in order to provide circuit parameter associated with temperature change in an IC as evidenced by “A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip … determining various important circuit parameters, environmental parameters of the IC chip (such as temperature), and/or operational conditions (such as power supply voltage) of the IC chip. The circuit parameters include process-dependent circuit parameters … sense elements include on-chip resistors of different values and types" (abstract, col. 1 lines 45-60 of Burns).
Regarding claim 2, Devadas in view of Burns teaches the method of claim 1, wherein the measuring the circuit parameter includes:
measuring resistance of multiple nominally identical integrated circuit resistors (149; fig. 9 of Devadas; 218,220 of figs. 2 of Burns) of the integrated circuit chip (50/209) of interest;
measuring resistance of a reference integrated circuit resistor of the integrated circuit chip of interest; and
calculating a ratio including the measured resistance of the multiple identical integrated circuit resistors and the measured resistance of the reference integrated circuit resistor (col. 15 lines 50-60 of Burns :- where: R' is R.sub.actual/R.sub.ideal, or a corresponding ratio of sheet-rhos) and including multiple measurements of the ratio in the individualized identifier for the integrated circuit chip of interest (para. 106 of Devadas - temperature of circuits in chip 50 increases due to resistive heating. Compensated PUF 149 is designed so that the circuits are heated uniformly during operation to ensure the stability of the ratio of the outputs of PUF circuit 101 and reference circuit 148).
Regarding claim 4, Devadas teaches in figure(s) 1-56 the method of claim 1, wherein the measuring the circuit parameter includes:
measuring a temperature coefficient of resistance (TCR) of multiple nominally identical resistance-temperature-detectors (RTDs) of the integrated circuit chip of interest;
measuring a TCR of a reference RTD of the integrated circuit chip of interest; and calculating a ratio including the measured TCR for the multiple identical RTDs and the TCR for the reference RTD as the circuit parameter to produce the individualized identifier for the integrated circuit chip of interest (para. 106 - temperature of circuits in chip 50 increases due to resistive heating. Compensated PUF 149 is designed so that the circuits are heated uniformly during operation to ensure the stability of the ratio of the outputs of PUF circuit 101 and reference circuit 148).
Regarding claim 5, Devadas teaches in figure(s) 1-56 the method of claim 1, wherein the measuring the circuit parameter includes: determining digital values of a ratio including a voltage of the multiple integrated circuit elements and a voltage of a reference integrated circuit element (para. 16 - computing a ratio of a measurement of the selected characteristic to a measurement of the reference characteristic; para. 104 - measurable characteristics in measurable component 102 may vary due to variations in environmental conditions, such as varying ambient temperature and power supply voltages); and producing the individualized identifier for the integrated circuit chip of interest using the determined digital values (para. 3 - generating a unique identifier is to incorporate an array of transistors in the chip, measure the threshold voltages of the transistors in the array, and output the measurements as the identifier).
Regarding claim 7, Devadas teaches in figure(s) 1-56 the method of claim 1, including: storing, in the identifier database, database entries including the identifiers of the multiple integrated circuits stored in association with manufacturing information of the multiple integrated circuits; and determining the manufacturing information of the specific integrated circuit according to the comparing of the individualized identifier for the integrated circuit chip of interest to the identifier database (para. 59 - Chip 50 is fabricated using a set of lithography masks that define the circuit patterns of chip 50. When the same lithography masks are used to produce a set of chips, due to slight variations in the manufacturing process, in general, no two chips are exactly alike. the functions performed by the functional module 52 remain the same for all chips made from the same set of lithography masks. PUF circuit 100, on the other hand, is designed to take advantage of the variations in the various parameters across different chips. The "function" of PUF circuit 100 is, in general, different for different chips fabricated using the same set of lithography masks. Different PUF circuits 100 fabricated using the same set of lithography masks in general map the same input to different outputs).
Regarding claim 8, Devadas in view of Burns teaches the method of claim 1, wherein the measuring the circuit parameter includes measuring the circuit parameter of multiple identical integrated circuit elements fabricated in a two-dimensional array on the integrated circuit chip of interest (para. 59 - There will be slight variations in various parameters (e.g., length and width of conducting wires, concentration of doping regions, thickness of dielectric layers) within each chip as well as across different chips; para. 345 - When a set of integrated circuit chips having clocked circuits are fabricated using a set of lithography masks, each chip is unique in its delay characteristics due to variations in manufacturing across different dies, wafers, and processes – implies 2D array of the integrated circuit) and
wherein the digital values are produced for each column or row of the two-dimensional array of integrated circuit elements (col. 11 lines 30-35 :- Sense element 506 may be any one of sense circuits 210-222, 250 and 270. Digitizer 112 digitizes sense signal 508 into digitized code 164) using a ratio metric analog-to-digital converter (ADC) circuit (ADC 112 in fig. 5 of Burns).
Regarding claim 9, Devadas teaches in figure(s) 1-56 An integrated circuit chip comprising:
multiple integrated circuit elements (elements of 50; figs. 1,9);
an analog-to-digital converter (ADC) circuit (para. 373 - functional circuitry and the PUF can reside on different semiconductor chips in a multi-chip module. The input and output of the PUF circuit may be analog values rather than digitized values; fig. 14); and logic circuitry (51) configured to: produce, using the ADC circuit, digital values representative of a circuit parameter of the multiple integrated circuit elements; and output an individualized identifier of the integrated circuit chip that includes the produced digital values (para. 303 - smartcard may be required to identify itself using a digital challenge-response protocol before the card reader challenges the smartcard with one of the limited number of CRPs that it has) produced for the multiple integrated circuit elements.
Devadas does not teach explicitly wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements.
However, Burns teaches in figure(s) 1-10 wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements (col. 1 lines 25-28 :- IC integrated circuits may be characterized in terms of various circuit parameters, such as sheet-rho; clms. 11,16 - measure of a first manufacturing process-dependent circuit parameter …wherein the first manufacturing process-dependent circuit parameter is a sheet resistance of a resistor disposed on the integrated circuit chip; figs. 1-3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements as taught by Burns in order to provide circuit parameter associated with temperature change in an IC as evidenced by “A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip … determining various important circuit parameters, environmental parameters of the IC chip (such as temperature), and/or operational conditions (such as power supply voltage) of the IC chip. The circuit parameters include process-dependent circuit parameters … sense elements include on-chip resistors of different values and types" (abstract, col. 1 lines 45-60 of Burns).
Regarding claim 10, Devadas teaches in figure(s) 1-56 the integrated circuit chip of claim 9, including: a reference integrated circuit element; and wherein the logic circuitry is configured to produce digital values representative of a ratio including the circuit parameter of the multiple integrated circuit elements and a circuit parameter of the reference integrated circuit element (para. 16 - computing a ratio of a measurement of the selected characteristic to a measurement of the reference characteristic; para. 104 - measurable characteristics in measurable component 102 may vary due to variations in environmental conditions, such as varying ambient temperature and power supply voltages).
Regarding claim 11, Devadas teaches in figure(s) 1-56 the integrated circuit chip of claim 10, wherein the multiple integrated circuit elements are multiple nominally identical integrated circuit resistors and the reference integrated circuit element is a reference integrated circuit resistor; and wherein the logic circuitry is configured to produce digital values representative of a ratio including a resistance of the multiple nominally identical integrated circuit resistors and a resistance of the reference integrated circuit resistor (para. 106 - temperature of circuits in chip 50 increases due to resistive heating. Compensated PUF 149 is designed so that the circuits are heated uniformly during operation to ensure the stability of the ratio of the outputs of PUF circuit 101 and reference circuit 148 – implies resistive ratio between under test and reference circuit).
Regarding claim 13, Devadas teaches in figure(s) 1-56 the integrated circuit chip of claim 10, wherein the multiple integrated circuit elements are multiple nominally identical resistance-temperature-detectors (RTDs) and the reference integrated circuit element is a reference RTD; and wherein the logic circuitry is configured to produce digital values representative of a ratio including a temperature coefficient of resistance (TCR) of the multiple nominally identical RTDs and a TCR of the reference RTD (para. 106 - temperature of circuits in chip 50 increases due to resistive heating. Compensated PUF 149 is designed so that the circuits are heated uniformly during operation to ensure the stability of the ratio of the outputs of PUF circuit 101 and reference circuit 148 – implies rtd ratio between under test and reference circuit).
Regarding claim 15, Devadas teaches in figure(s) 1-56 the integrated circuit chip of claim 9, wherein the multiple integrated circuit elements are arranged in a two-dimensional array of the integrated circuit elements on the integrated circuit chip; wherein the ADC circuit is one of multiple ratio-metric ADC circuits included in the integrated circuit chip; and wherein each ratio-metric ADC circuit produces the digital values for one column or row of the two-dimensional array of the integrated circuit elements (para. 59 - There will be slight variations in various parameters (e.g., length and width of conducting wires, concentration of doping regions, thickness of dielectric layers) within each chip as well as across different chips; para. 345 - When a set of integrated circuit chips having clocked circuits are fabricated using a set of lithography masks, each chip is unique in its delay characteristics due to variations in manufacturing across different dies, wafers, and processes – implies 2D array of the integrated circuit).
Regarding claim 16, Devadas teaches in figure(s) 1-56 the integrated circuit of claim 9, wherein the integrated circuit chip excludes a memory circuit (chip 50 does not include memory in fig. 9).
Regarding claim 17, Devadas teaches in figure(s) 1-56 An electronic device comprising:
a memory (storage 220; fig. 32) configured to store an identifier database (para. 291 - a storage 220 for storing challenge-response pairs CRPs) including identifiers of multiple integrated circuit chips, wherein the identifiers include measurements of a circuit parameter (physical unique function PUF circuit 209) of multiple integrated circuit elements of each of the multiple integrated circuit chips (208; para. 291 - smartcard 206 includes an integrated circuit chip 208 that has a PUF circuit 209);
a port (port 212) to receive an individualized identifier (physical unique function PUF circuit 209) for an integrated circuit chip of interest, wherein the individualized identifier includes measurements of a circuit parameter of multiple integrated circuit elements of the integrated circuit chip of interest (step 372 in fig. 33; para. 293 - a set of CRPs for that smartcard using process 602 (FIG. 27). The CRPs is stored in a secured database); and
a processor (218) operatively coupled to the memory and the port, wherein the processor is configured to:
compare the individualized identifier to identifiers of the identifier database;
identify the integrated circuit chip of interest as a specific integrated circuit of the identifier database using the comparison (para. 291 - Processor 218 processes the message to generate the response, compares the response received from the smartcard with the response stored in storage 220 associated with the challenge. When the responses match, smartcard 206 is authenticated.); and
present manufacturing information of the integrated circuit chip of interest according to the comparison of the individualized identifier to the identifier database (para. 342 - fuse bits are set while the chip is in testing by the manufacturer. An initialization circuit 718 receives the key K from the manufacturer through line 720, and receives the response from PUF circuit 100 through line 722. Initialization circuit 718 calculates the fuse bits that is needed to generate the correct key K, and bums the fuses 708 accordingly).
Devadas does not teach explicitly wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements.
However, Burns teaches in figure(s) 1-10 wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements (col. 1 lines 25-28 :- IC integrated circuits may be characterized in terms of various circuit parameters, such as sheet-rho; clms. 11,16 - measure of a first manufacturing process-dependent circuit parameter …wherein the first manufacturing process-dependent circuit parameter is a sheet resistance of a resistor disposed on the integrated circuit chip; figs. 1-3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the circuit parameter includes a resistance parameter of the multiple integrated circuit elements as taught by Burns in order to provide circuit parameter associated with temperature change in an IC as evidenced by “A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip … determining various important circuit parameters, environmental parameters of the IC chip (such as temperature), and/or operational conditions (such as power supply voltage) of the IC chip. The circuit parameters include process-dependent circuit parameters … sense elements include on-chip resistors of different values and types" (abstract, col. 1 lines 45-60 of Burns).
Regarding claim 18, Devadas teaches in figure(s) 1-56 the electronic device of claim 17, wherein the identifier database includes measured resistance ratios of the multiple integrated circuit chips, wherein the resistance ratios are ratios that include resistance of multiple integrated circuit resistors of an integrated circuit chip and resistance of a reference integrated circuit resistor of the integrated circuit chip; and wherein the processor is configured to compare, as the individualized identifier, measured resistance ratios of the of the integrated circuit of interest to the measured resistance ratios of the identifier database to identify the specific integrated circuit chip of the identifier database (para. 106 - temperature of circuits in chip 50 increases due to resistive heating. Compensated PUF 149 is designed so that the circuits are heated uniformly during operation to ensure the stability of the ratio of the outputs of PUF circuit 101 and reference circuit 148).
Regarding claim 20, Devadas teaches in figure(s) 1-56 the electronic device of claim 17, wherein the identifier database includes measured temperature coefficient of resistance (TCR) ratios of the multiple integrated circuit chips, wherein the TCR ratios are ratios that include the TCR of multiple resistance-temperature-detectors (RTDs) of an integrated circuit chip and a TCR of a reference RTD of the integrated circuit chip; and wherein the processor is configured to compare, as the individualized identifier, measured TCR ratios of the of the integrated circuit of interest to the measured TCR ratios of the identifier database to identify the specific integrated circuit chip of the identifier database (para. 106 - temperature of circuits in chip 50 increases due to resistive heating. Compensated PUF 149 is designed so that the circuits are heated uniformly during operation to ensure the stability of the ratio of the outputs of PUF circuit 101 and reference circuit 148 – implies rtd ratio between under test and reference circuit).
Claim(s) 3, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Devadas in view of Burns, and further in view of Hamilton et al. (US 20150219714).
Regarding claim 3, Devadas in view of Burns teaches the method of claim 1,
Devadas does not teach explicitly wherein the measuring the circuit parameter includes:
measuring capacitance of multiple nominally identical capacitors of the integrated circuit chip of interest;
measuring capacitance of a reference capacitor of the integrated circuit chip of interest; and
calculating a ratio including the measured capacitance of the multiple identical capacitors and the measured capacitance of the reference capacitor as the circuit parameter to produce the individualized identifier for the integrated circuit chip of interest.
However, Hamilton teaches in figure(s) 1-8 wherein the measuring the circuit parameter includes:
measuring capacitance of multiple nominally identical capacitors of the integrated circuit chip of interest;
measuring capacitance of a reference capacitor of the integrated circuit chip of interest; and
calculating a ratio including the measured capacitance of the multiple identical capacitors and the measured capacitance of the reference capacitor as the circuit parameter to produce the individualized identifier for the integrated circuit chip of interest (para. 29 - predetermined percentage variation can also be selected based on a determination of a segment of the DUT IC's capacitance curve plot having a zero slope change or a smallest change in slope values (rise over run) between at least two capacitance data measurements… capacitance value can be based on a three standard deviation measure derived from capacitance measurement data produced from testing known-good parts having identical part numbers or identifiers in a selected lot to produce a desired predetermined percentage variation or nearly the same capacitance value measure).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the measuring the circuit parameter includes: measuring capacitance of multiple nominally identical capacitors of the integrated circuit chip of interest; measuring capacitance of a reference capacitor of the integrated circuit chip of interest; and calculating a ratio including the measured capacitance of the multiple identical capacitors and the measured capacitance of the reference capacitor as the circuit parameter to produce the individualized identifier for the integrated circuit chip of interest as taught by Hamilton in order to provide "wherein by sweeping the alternating current signal across a specified frequency range one or more capacitance related device signature can be created and used to identify a component as originating from a trusted source or not" (abstract).
Regarding claim 12, Devadas in view of Burns teaches the integrated circuit chip of claim 10,
Devadas does not teach explicitly wherein the multiple integrated circuit elements are multiple nominally identical capacitors and the reference integrated circuit element is a reference capacitor; and wherein the logic circuitry is configured to produce digital values representative of a ratio including a capacitance of the multiple nominally identical capacitors and a capacitance of the reference capacitor.
However, Hamilton teaches in figure(s) 1-8 wherein the multiple integrated circuit elements are multiple nominally identical capacitors and the reference integrated circuit element is a reference capacitor; and wherein the logic circuitry is configured to produce digital values representative of a ratio including a capacitance of the multiple nominally identical capacitors and a capacitance of the reference capacitor (para. 29 - predetermined percentage variation can also be selected based on a determination of a segment of the DUT IC's capacitance curve plot having a zero slope change or a smallest change in slope values (rise over run) between at least two capacitance data measurements… capacitance value can be based on a three standard deviation measure derived from capacitance measurement data produced from testing known-good parts having identical part numbers or identifiers in a selected lot to produce a desired predetermined percentage variation or nearly the same capacitance value measure – implies capacitive ratio between under test and reference circuit).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the multiple integrated circuit elements are multiple nominally identical capacitors and the reference integrated circuit element is a reference capacitor; and wherein the logic circuitry is configured to produce digital values representative of a ratio including a capacitance of the multiple nominally identical capacitors and a capacitance of the reference capacitor as taught by Hamilton in order to provide "wherein by sweeping the alternating current signal across a specified frequency range one or more capacitance related device signature can be created and used to identify a component as originating from a trusted source or not" (abstract).
Regarding claim 19, Devadas in view of Burns teaches the electronic device of claim 17,
Devadas does not teach explicitly wherein the identifier database includes measured capacitance ratios of the multiple integrated circuit chips, wherein the capacitance ratios are ratios that include capacitance of multiple capacitors of an integrated circuit chip and capacitance of a reference capacitor of the integrated circuit chip; and wherein the processor is configured to compare, as the individualized identifier, measured capacitance ratios of the of the integrated circuit of interest to the measured capacitance ratios of the identifier database to identify the specific integrated circuit chip of the identifier database.
However, Hamilton teaches in figure(s) 1-8 wherein the identifier database includes measured capacitance ratios of the multiple integrated circuit chips, wherein the capacitance ratios are ratios that include capacitance of multiple capacitors of an integrated circuit chip and capacitance of a reference capacitor of the integrated circuit chip; and wherein the processor is configured to compare, as the individualized identifier, measured capacitance ratios of the of the integrated circuit of interest to the measured capacitance ratios of the identifier database to identify the specific integrated circuit chip of the identifier database (para. 29 - predetermined percentage variation can also be selected based on a determination of a segment of the DUT IC's capacitance curve plot having a zero slope change or a smallest change in slope values (rise over run) between at least two capacitance data measurements… capacitance value can be based on a three standard deviation measure derived from capacitance measurement data produced from testing known-good parts having identical part numbers or identifiers in a selected lot to produce a desired predetermined percentage variation or nearly the same capacitance value measure – implies capacitive ratio between under test and reference circuit).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the identifier database includes measured capacitance ratios of the multiple integrated circuit chips, wherein the capacitance ratios are ratios that include capacitance of multiple capacitors of an integrated circuit chip and capacitance of a reference capacitor of the integrated circuit chip; and wherein the processor is configured to compare, as the individualized identifier, measured capacitance ratios of the of the integrated circuit of interest to the measured capacitance ratios of the identifier database to identify the specific integrated circuit chip of the identifier database as taught by Hamilton in order to provide "wherein by sweeping the alternating current signal across a specified frequency range one or more capacitance related device signature can be created and used to identify a component as originating from a trusted source or not" (abstract).
Claim(s) 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Devadas in view of Burns, and further in view of Fiori et al. (US 9995778).
Regarding claim 6, Devadas in view of Burns teaches the method of claim 5,
Devadas does not teach explicitly wherein the determining the digital values of the ratio includes determining the digital values of the ratio using a ratio-metric analog-to-digital converter (ADC) circuit.
However, Fiori teaches in figure(s) 1-10 wherein the determining the digital values of the ratio includes determining the digital values of the ratio using a ratio-metric analog-to-digital converter (ADC) circuit (col. 17 lines 20-30 - measurement of that amplified potential is then carried out most cost effectively with a ratio-metric analog to digital converter which would be incorporated in a modern micro-controller integrated circuit that may be used to implement Logic; fig. 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having wherein the determining the digital values of the ratio includes determining the digital values of the ratio using a ratio-metric analog-to-digital converter (ADC) circuit as taught by Fiori in order to provide "develop their readings in relation to the ratio of the applied voltage and possibly the same power supply rail potential or at least a fixed proportion of that power supply rail potential. The result is a reading of the temperature which is insensitive to the power supply rail potential, and without requiring a precision voltage source to develop accurate temperature measurements" (abstract).
Regarding claim 14, Devadas in view of Burns teaches the integrated circuit chip of claim 10,
Devadas does not teach explicitly including: wherein the ADC circuit is a ratio-metric ADC circuit and the logic circuitry is configured to: produce a voltage on the multiple integrated circuit elements; produce a voltage on the reference integrated circuit element; and produce digital values representative of a ratio including the voltage of a reference integrated circuit element and the voltage of an integrated circuit element of the multiple integrated circuit elements.
However, Fiori teaches in figure(s) 1-10 including: wherein the ADC circuit is a ratio-metric ADC circuit and the logic circuitry is configured to: produce a voltage on the multiple integrated circuit elements; produce a voltage on the reference integrated circuit element; and produce digital values representative of a ratio including the voltage of a reference integrated circuit element and the voltage of an integrated circuit element of the multiple integrated circuit elements (col. 17 lines 20-30 - measurement of that amplified potential is then carried out most cost effectively with a ratio-metric analog to digital converter which would be incorporated in a modern micro-controller integrated circuit that may be used to implement Logic; fig. 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Devadas by having including: wherein the ADC circuit is a ratio-metric ADC circuit and the logic circuitry is configured to: produce a voltage on the multiple integrated circuit elements; produce a voltage on the reference integrated circuit element; and produce digital values representative of a ratio including the voltage of a reference integrated circuit element and the voltage of an integrated circuit element of the multiple integrated circuit elements as taught by Fiori in order to provide "develop their readings in relation to the ratio of the applied voltage and possibly the same power supply rail potential or at least a fixed proportion of that power supply rail potential. The result is a reading of the temperature which is insensitive to the power supply rail potential, and without requiring a precision voltage source to develop accurate temperature measurements" (abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKM ZAKARIA/Primary Examiner, Art Unit 2858
Prosecution Insights