DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, (Species IB (Fig. 3A-3F); Claims 1, 2, 15-19) in the reply filed on 06/15/2026 and during phone interview on 08/15/2026 is acknowledged.
The traversal is on the ground(s) that. “Because amended claim 1 and amended claim 27 have unity of invention, claims 2, 15-21 and 24-25 depends on amended claim 1, and claims 28-30, 32-34 and 36-37 depend on amended claim 27, claims 1-2, 15-21, 24-25 and 27, 28-30, 32-34 and 36-37 can be searched and examined together as these two groups of claims relate to a single general inventive concept under PCT rule 13.1 and have unity of invention.”
This is not found persuasive because the groups of inventions listed in REQUIREMENT FOR UNITY OF INVENTION from 04/15/2026 do not relate to a single general inventive concept under PCT Rule 13.1 because, under PCT Rule 13.2, they lack the same or corresponding special technical features for the following reasons: Groups I, II and III lack unity of invention because even though the inventions of these groups require of a gate insulating layer, located on a side of the gate electrode layer; an active structure, located on a side of the gate insulating layer away from the gate electrode layer; and a source/drain electrode layer, located on a side of the active structure away from the gate insulating layer and/or the composite etching solution comprises a first etching solution and a second etching solution is not a special technical feature as it does not make a contribution over the prior art in view of Kong et aI. (CN 113889434 A)
The requirement is still deemed proper and is therefore made FINAL.
Claims 20-21, 24-25 and 27, 28-30, 32-34 and 36-37 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Groups, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 06/15/2026
Claim Objections
Claim 2 is objected to because of the following informalities:
Claim 2 recites “the overlapping regions of the active structure comprises an overlapping part of the active layer”. Plural “regions” paired with singular comprises” introduces grammatical informality. The Examiner recommends correction to “comprise” for clarity and consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 16-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “oxidizing a portion of the active structure material layer through the first etching solution, and etching an oxidized portion of the active structure material layer”.
It is unclear whether “an oxidized portion” refers back to the previously recited oxidized portion or introduces a separate, additional portion. This renders claim indefinite.
For the purposes of examination, the Examiner will treat “an oxidized portions” as –the oxidized portion--.
Claims 2 and 15-19 are rejected as being dependent on Claim 1.
Claim 16 recites “a surface of the source/drain material layer away from the active structure material layer is partially exposed before the wet etching process is performed”
It is unclear whether “the wet etching process” refers back to the previously recited single wet etching process or introduces a separate, additional wet etching process. This renders claim indefinite.
For the purposes of examination, the Examiner will treat “the wet etching process” as –the single wet etching process--.
Claim 18 recites “performing a dry etching process on the active structure material layer by using the patterned mask layer and the source/drain material layer as an etching mask, after the initial wet etching process and before the wet etching process using the composite etching solution.”
Claim 1 requires the source/drain material layer and the active structure material layer be patterned into the final source/drain electrode layer and active structure by “a single wet etching process” as in one wet etching accomplishes the patterning of both layers together. Claim 18, however, recites an additional dry etching process performed specifically “on the active structure material layer” that occurs specifically “on the active structure material layer” that occurs before the composite etching solution single wet etch of claim 1.
As drafted, it is unclear whether: this dry etching process removes or patterns a portion of the same active structure material layer region that claim 1 requires to be patterned exclusively by the single wet etching process which would directly conflict with Claim 1 single wet etching process limitation
or
This dry etching process is directed to a different region of the active structure material layer (material located outside the thin film transistor) describing an over etch separate from channel defining pattern.
Claim 19 recites the limitation "the active structure layer " in line 6. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, the Examiner will treat "the active structure layer " as --the active structure material layer--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (CN 114164003 A; Filed 12/06/21, Published 11/03/2022) in view of Kwon et al. (KR 101939385 B1; Published 01/16/2019) and Oishi et al. (US 7,476,898 B2).
Regarding Claim 1, He (Fig. 1, 4) discloses a method of manufacturing a thin film transistor device, comprising:
forming a gate electrode layer (102) on a base substrate (100);
forming a gate insulating layer (104) on a side of the gate electrode layer (102);
forming an active structure material layer (106, 108) on a side of the gate insulating layer away from the gate electrode layer (102), wherein
the active structure material layer (106, ohmic contact 108) comprises an active material layer (106) and an ohmic contact material layer (108), and the ohmic contact material layer (108) is formed on a side of the active material layer (106) away from the gate insulating layer (104);
forming a source/drain material layer (110) on a side of the active structure material layer (106, 108) away from the gate insulating layer (104); and
performing a single wet etching process on the source/drain material layer (110) and the active structure material layer (106, 108) by using a patterned mask layer (“patterned photoresist layer”) as an etching mask and using a composite etching solution, so as to pattern the source/drain material layer (110) and the active structure material layer (106, 108) into a source/drain electrode layer and an active structure,
“only one wet etching process, can remove the ohmic contact 108 and electrode layer 110 is not contact layer 108 and electrode layer 110 shielding part (especially located in the channel part). and removing a portion of the surface of the semiconductor layer 106 which is not shielded by the patterned photoresist layer (not shown). The wet etching process can be used for disposable, the remove layer 110 exposed by the patterned photoresist layer, the part of the contact layer 108 and the semiconductor layer 106. In the above wet etching process, the patterned semiconductor layer 106, the contact layer 108 and the electrode layer 110 are formed, and the patterned electrode layers 110 on the opposite sides of the channel respectively as the drain electrode and the source electrode”
wherein
the composite etching solution comprises a first etching solution and a second etching solution, and
“the etchant composition capable of simultaneously etching the metal layer and the silicon-containing non-metal layer, comprising: An etchant composition for display panel, wherein it is composed of the following raw materials by weight percentage: 5 % to 15 % of hydrogen peroxide, 0.1 % to 1 % of etching inhibitor, 2 % to 10 % of etching additive, 1 % to 5 % of pH value regulator, 0.01 % to 1.0 % of fluoride and the rest of aqueous medium, the etchant composition can be used for simultaneously etching the metal layer in the display panel and the silicon-containing non-metal layer adjacent to the metal layer.”
the wet etching process comprises:
etching the source/drain material layer (110) through the first etching solution, and etching the active structure material layer (106, 108) through the second etching solution, wherein
the active structure comprises an active layer (106) and an ohmic contact layer (108), and the active structure has overlapping regions (regions of 106, 108 overlapping under 110), a channel region (region of 106 between regions of 110) , wherein
the overlapping regions (regions of 106, 108 overlapping under 110) overlap with the source/drain electrode layer (110) in a direction perpendicular to a main surface of the base substrate (100), the channel region (region of 106 between regions of 110) is located between the overlapping regions (regions of 106, 108 overlapping under 110) , wherein
the ohmic contact layer (108) is located in the overlapping regions (regions of 106, 108 overlapping under 110), and in the direction perpendicular to the main surface of the base substrate (100), an orthographic projection of the ohmic contact layer (108) on the base substrate (100) is located within a range of an orthographic projection of the source/drain electrode layer (110) on the base substrate (100). (Fig. 1, 4)
He does not explicitly disclose oxidizing a portion of the active structure material layer through the first etching solution, and etching an oxidized portion of the active structure material layer through the second etching solution and a tailing region and the tailing region laterally extends beyond an edge of the source/drain electrode layer away from the channel region in a direction parallel to the main surface of the base substrate.
Kwon (Fig. 3) discloses oxidizing a portion of an active structure material layer (24) through a first etching solution (“hydrogen peroxide”), and etching an oxidized portion of the active structure material layer through a second etching solution (fluorine-containing compound)
“In the etchant composition used in the present invention, hydrogen peroxide not only acts as an oxidizing agent directly participating in etching, but also enhances the activity of the fluorine-containing compound.”…”In the etching solution composition of the present invention, the fluorine-containing compound means a compound dissociated in water and capable of emitting F .sup.- ions. The fluorine-containing compound is a main component for etching the source / drain electrode layer 22 ', the n + doping layer 25, and the active layer 24, and removes residues generated during the etching process.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of manufacturing a thin film transistor device in He in view of Kwon such that a portion of the active structure material layer through the first etching solution, and etching an oxidized portion of the active structure material layer through the second etching solution in order enhance the process margin and maintain consistent etch rate (Kwon)
He in view of Kwon does not explicitly disclose a tailing region and the tailing region laterally extends beyond an edge of the source/drain electrode layer away from the channel region in a direction parallel to the main surface of the base substrate.
Oishi (Fig. 4) discloses a tailing region (4A) and the tailing region (4A) laterally extends beyond an edge of a source/drain electrode layer (6A, 6B) away from a channel region (region of 4 between 6A and 6B) in a direction parallel to a main surface of a base substrate. (1) [column 6, lines 32-67]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of manufacturing a thin film transistor device in He in view of Kwon and Oishi such that a tailing region and the tailing region laterally extends beyond an edge of the source/drain electrode layer away from the channel region in a direction parallel to the main surface of the base substrate in order to suppress the leakage current of the TFT. [column 6, lines 52-67].
Regarding Claim 2, He in view of Kwon and Oishi discloses the method of manufacturing the thin film transistor device according to claim 1, wherein
the overlapping regions of the active structure (regions of 106, 108 overlapping under 110) comprises an overlapping part of the active layer (106), and the ohmic contact layer (108) located between the overlapping part and the source/drain electrode layer (110); the channel region comprises a channel part (part of 106 between regions of 110) of the active layer (106), the tailing region (4A, Oishi) comprises a tailing part of the active layer (4, oishi)), and neither the channel region (region of 106 between regions of 110) nor the tailing region (4A) comprises the ohmic contact layer (108, He; 5, Oishi).
Regarding Claim 15, He in view of Kwon and Oishi discloses the method of manufacturing the thin film transistor device according to claim 1, wherein
the first etching solution ( hydrogen peroxide )and the second etching solution (fluoride) in the composite etching solution are mixed with each other, and
the source/drain material layer (110) and the active structure material layer (106, 108) are etched in a single wet etching process.
“the etchant composition capable of simultaneously etching the metal layer and the silicon-containing non-metal layer, comprising: An etchant composition for display panel, wherein it is composed of the following raw materials by weight percentage: 5 % to 15 % of hydrogen peroxide, 0.1 % to 1 % of etching inhibitor, 2 % to 10 % of etching additive, 1 % to 5 % of pH value regulator, 0.01 % to 1.0 % of fluoride and the rest of aqueous medium, the etchant composition can be used for simultaneously etching the metal layer in the display panel and the silicon-containing non-metal layer adjacent to the metal layer.”
Regarding Claim 19, He in view of Kwon and Oishi discloses the method of manufacturing the thin film transistor device according to claim 2, wherein
after performing the wet etching process, further comprising:
removing the patterned mask layer (“patterned photoresist layer”); and
forming an insulating layer (112) (7) to cover sidewalls of the source/drain electrode (110) (6A,6B) layer and the active structure layer (108, 106) (4A, 5)as well as surfaces thereof away from the gate insulating layer (104) (3), wherein
surfaces of the channel part (part between regions of 106, 108 overlapping under 110) and the tailing part of the active layer (4A, Oishi) away from the gate insulating layer (104) are in contact with the insulating layer (112); and
a contact area between the insulating layer (112) and the channel part and between the insulating layer (112) and the tailing part (4A, Oishi), is substantially equal to an area of the surfaces of the channel part (part between regions of 106, 108 overlapping under 110) (part between regions of 6A,6B overlapping under 110) and the tailing part (4A, Oishi) away from the gate insulating layer (104) (3).
The Examiner notes that since the Applicant did not explicitly defined metes and bounds of “a contact area between the insulating layer and the channel part and between the insulating layer and the tailing part “ and “an area of the surfaces of the channel part” the Examiner selected areas of the insulating layer, the channel part and the tailing part to meet claim limitations.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (CN 114164003 A; Filed 12/06/21, Published 11/03/2022) in view of Kwon et al. (KR 101939385 B1; Published 01/16/2019) and Oishi et al. (US 7,476,898 B2) and further in view Takanashi et al. (US 2010/0059749 A1).
Regarding Claim 16, He in view of Kwon and Oishi discloses the method of manufacturing the thin film transistor device according to claim 1, wherein
He in view of Kwon and Oishi does not explicitly disclose the patterned mask layer comprises a plurality of mask patterns spaced apart from each other, and a surface of the source/drain material layer away from the active structure material layer is partially exposed before the wet etching process is performed, and an edge of the source/drain material layer laterally extends beyond an edge of the patterned mask layer in the direction parallel to the main surface of the base substrate.
Takanashi (Fig. 6, 7) discloses a patterned mask layer (123) comprises a plurality of mask patterns spaced apart from each other, and a surface of a source/drain material layer (119) away from an active structure material layer (115, 117) is partially exposed before etching process is performed, and an edge of a source/drain material layer (119) laterally extends beyond an edge of the patterned mask layer (123) in the direction parallel to a main surface of the base substrate. (101) (Fig. 6C)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of manufacturing a thin film transistor device in He in view of Kwon, Oishi and Takanashi such that the patterned mask layer comprises a plurality of mask patterns spaced apart from each other, and a surface of the source/drain material layer away from the active structure material layer is partially exposed before the wet etching process is performed, and an edge of the source/drain material layer laterally extends beyond an edge of the patterned mask layer in the direction parallel to the main surface of the base substrate in order to form a separated resist masks for forming source electrode layer and drain electrode layer [0139-0141]
Regarding Claim 17, He in view of Kwon, Oishi and Takanashi discloses the method of manufacturing the thin film transistor device according to claim 16, wherein before the wet etching process, further comprising:
forming an initial mask layer (121 Takanashi) on a side of the source/drain material layer (119, Takashi) away from the active structure material layer (115, 117 Takashi), wherein
the initial mask layer comprises a first mask pattern region (thicker region of 121) and a second mask pattern region (thinner region of 121), and
a thickness of the first mask pattern region is greater than a thickness of the second mask pattern region. (See Fig. 6B of Takashi)
Allowable Subject Matter
Claim 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY YEMELYANOV/ Examiner, Art Unit 2891
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