Prosecution Insights
Last updated: July 17, 2026
Application No. 18/681,388

MULTILAYER PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR PACKAGING MULTILAYER ASSEMBLY

Non-Final OA §102
Filed
Feb 05, 2024
Priority
Aug 06, 2021 — CN 202110901762.9 +1 more
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Unisoc (Shanghai) Technologies Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
669 granted / 867 resolved
+9.2% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
34 currently pending
Career history
888
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
58.6%
+18.6% vs TC avg
§102
11.8%
-28.2% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6-13 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dudderar et al. (US Pat 6,297,551, hereinafter Dudderar). Regarding claim 1, figure 1 of Dudderar discloses a multilayer package-on-package (PoP) assembly, comprising at least two circuit boards (14, 33), wherein an interposer (16) is disposed between two adjacent circuit boards of the at least two circuit boards, and a shield (25) is disposed on an upper contact surface and/or a lower contact surface of the interposer in contact with the at least two circuit boards; and electrical elements (18) on a corresponding contact surface are all surrounded (peripherally) by the shield, and a height of the shield is not less than a height of each of the electrical elements. Regarding claim 2, figure 1 of Dudderar discloses a shield coating (21/27), formed based on an electromagnetic interference (EMI) coating process, on an outer surface of the multilayer PoP assembly; wherein the shield coating and the shield (25) form a shield assembly of the multilayer PoP assembly. Regarding claim 3, figure 1 of Dudderar discloses the shield (25) is connected to the interposer (16) by pasting or soldering (col. 3, line 65 – col. 3, line 2); or in response to the height of the shield being less than a preset value, the shield is formed on the interposer by electroplating. Regarding claim 4, figure 1 of Dudderar discloses a material of the shield (25) comprises a conductive metal (col. 3, line 65 – col. 3, line 2). Regarding claim 6, figure 1 of Dudderar discloses a shape of the shield (25) comprises any one of a hollow circle, a hollow square, and a hollow rectangle. Regarding claim 7, figure 1 of Dudderar discloses the height of the shield (25) equals to a height of an electrical element (18) having a maximum height among the electrical elements. Regarding claim 8, figure 1 of Dudderar discloses a circuit structure of each of the electrical elements (18) is a copper pad, a solder joint, or a solder ball. Regarding claim 9, figure 1 of Dudderar discloses the shield coating (21/27) is physically connected to the shield (25). Regarding claim 10, figure 1 of Dudderar discloses a shape of the shield (25) is determined according to shapes of the at least two circuit boards and distribution of the electrical elements on the circuit board and the interposer. Regarding claim 11, figure 1 of Dudderar discloses a method for packaging a multilayer assembly, wherein the multilayer assembly comprises at least two circuit boards, and the method comprises: disposing a shield (25) on an upper contact surface and/or a lower contact surface of an interposer (16), wherein electrical elements (18) on a corresponding contact surface are all surrounded by the shield, and a height of the shield is not less than a height of each of the electrical elements; disposing an interposer (16) between any two adjacent circuit boards (14, 33) of the at least two circuit boards; and forming, based on an electromagnetic interference (EMI) coating process (col. 3, lines 3-12), a shield coating (21/27) on an outer surface of the multilayer assembly and on an outer surface the interposer. Regarding claim 12, figure 1 of Dudderar discloses prior to disposing the shield (25) on the upper contact surface and/or the lower contact surface of the interposer (16), the method further comprises: obtaining a maximum height of the electrical elements (18) on the corresponding contact surface; and forming the shield having the height that is not less than the maximum height. Regarding claim 13, figure 1 of Dudderar discloses disposing the shield (25) on the upper contact surface and/or the lower contact surface of the interposer (16) specifically comprises: pasting or soldering the shield to the corresponding contact surface (col. 3, line 65 – col. 3, line 2). Regarding claim 15, figure 1 of Dudderar discloses a material of the shield (25) comprises a conductive metal (col. 3, line 65 – col. 3, line 2). Regarding claim 16, figure 1 of Dudderar discloses a shape of the shield (25) comprises any one of a hollow circle, a hollow square, and a hollow rectangle. Regarding claim 17, figure 1 of Dudderar discloses the height of the shield (25) equals to a height of an electrical element (18) having a maximum height among the electrical elements. Regarding claim 18, figure 1 of Dudderar discloses a circuit structure of each of the electrical elements (18) is a copper pad, a solder joint, or a solder ball. Regarding claim 19, figure 1 of Dudderar discloses the shield coating (21/27) is physically connected to the shield (25). Regarding claim 20, figure 1 of Dudderar discloses a shape of the shield (25) is determined according to shapes of the at least two circuit boards (14, 33) and distribution of the electrical elements (18) on the circuit board and the interposer (16). Allowable Subject Matter Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Feb 05, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685229
SELECTIVE WIRE COATING DURING WIRE BONDING
2y 11m to grant Granted Jul 14, 2026
Patent 12685186
CAVITIES IN PACKAGE CONDUCTIVE TERMINALS
2y 8m to grant Granted Jul 14, 2026
Patent 12677670
CIRCUIT MODULE
3y 3m to grant Granted Jul 07, 2026
Patent 12677692
INSULATION LAYER FOR A SEMICONDUCTOR PACKAGE
2y 11m to grant Granted Jul 07, 2026
Patent 12677433
METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH PROTECTION LAYER
2y 9m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
86%
With Interview (+8.5%)
2y 8m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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