Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the applicant’s arguments related to the election/restriction dated 06/08/2026, it is noted that the applicant elects invention I, claims 16-31, with traverse. Additionally, as applicant noted, the application is a National Stage application under 35 U.S.C. 371, which is evaluated on unity of invention. In response, the office asserts that the restriction is maintained as even under the unity of invention analysis, as the device of invention I has a special technical skill related to the specifics of the first and second junctions in combination with the helper games while invention II has a special technical skill related to use with magnetic field being applied to the channel region. As noted in the original election/restriction, the use of the magnetic field is not required for using the specific device and its structural components as claimed. The restriction under unity of invention is maintained because as described above the two inventions have different special technical features not seen by the other one.
Claims 16-31 are examined upon the merits below. If rejoinder would be desired at the conclusion of prosecution, Applicant is reminded that the method must include in the operation, all the structural features of the device of claim 16, so it is clear all the structural limitations of claim 16 are required by the method claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, 18-21, 23, 25, and 28-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hart et al (US 20200321508) in view of Freedman et al (US 20180053809).
Regarding claim 16, Hart et al teaches
[claim 16] A semiconductor-superconductor hybrid device, comprising:
a superconductor component arranged over the semiconductor component, the superconductor component being capable of inducing superconductivity in a channel region of the semiconductor component by proximity effect (figure 6, paragraph 0070, where element 606 is the semiconductor component, element 604 is the superconducting component arranged over the semiconductor component and can induce superconductivity by the proximity effect through the semiconductor channel),
wherein the superconductor component comprises an elongate strip of superconductor material having two ends, at least one of the ends being electrically grounded (figure 6, paragraphs 0069 and 0074, where element 604 is the superconductor elongated strip having two ends, with one end being connected to ground – as shown in figure 4 where the ground planes are also part of the superconducting component),
However, Hart et al does not specifically disclose
[claim 16] a semiconductor component configured to host a 2-dimensional electron gas or a 2- dimensional hole gas; and a set of depletion gates arranged over the semiconductor component, the set of depletion gates being configured to define boundaries of the channel region by depleting charge carriers from regions of the semiconductor component along edges of the channel region, wherein the set of depletion gates comprises: at least one first outer depletion gate for defining a first outer segment of the channel region; at least one second outer depletion gate for defining a second outer segment of the channel region; and at least one inner depletion gate for defining an inner segment of the channel region between the first outer segment and the second outer segment; wherein the device further comprises: a first junction comprising a first space between the at least one first outer depletion gate and the at least one inner depletion gate, and a first helper gate for gating the first space; a second junction comprising a second space between the at least one second outer depletion gate and the at least one inner depletion gate, and a second helper gate for gating the second space; and wherein the first and second helper gates are each operable to connect electrically the channel region to respective leads.
However, Freeman et al does teach
[claim 16] a semiconductor component configured to host a 2-dimensional electron gas or a 2- dimensional hole gas (paragraph 0045, where the semiconductor components are configured to hose a 2DEG electron gas),
and a set of depletion gates arranged over the semiconductor component, the set of depletion gates being configured to define boundaries of the channel region by depleting charge carriers from regions of the semiconductor component along edges of the channel region (figure 3, paragraphs 0033-0035, where the depletion gates are the gates on element 314 arranged left to right, defining channel regions in the superconductor material [element 310] from left to right by depletion of charge carries from regions of the semiconductor component [element 314] along the edges of the channel [each channel is element 310 that spans left to right between each section of semiconductor wife [element 314]]),
wherein the set of depletion gates comprises: at least one first outer depletion gate for defining a first outer segment of the channel region; at least one second outer depletion gate for defining a second outer segment of the channel region (figure 3, paragraphs 0033-0035, where the first outer depletion gate is the gate on the left-hand side of figure 3, on element 314 and defines the first outer segment of the channel region [situated between element 314 on the left and middle], and a second outer depletion gate [right hand side of figure 3 on element 314] defining a second outer segment of the channel region [situated between middle element 314 and right-hand side element 314]);
and at least one inner depletion gate for defining an inner segment of the channel region between the first outer segment and the second outer segment (figure 3, paragraphs 0033-0035, where element 314 comprises the inner segment of the channel region and has a depletion gate on element 314 situated between the first outer segment [left-hand side] and the second outer segment [right-hand side]);
wherein the device further comprises: a first junction comprising a first space between the at least one first outer depletion gate and the at least one inner depletion gate, and a first helper gate for gating the first space (figure 3, paragraph 0033-0035, where the gate situated on element 310 between element 314 depletion gate on the left-hand side [first outer depletion gate] and the inner depletion gate [depletion gate on element 314 in the middle] and with a first helper gate [gate situated on element 310 between the first outer and second outer depletion gates);
a second junction comprising a second space between the at least one second outer depletion gate and the at least one inner depletion gate, and a second helper gate for gating the second space (figure 3, paragraph 0033-0035, where the gate situated on element 310 between element 314 depletion gate on the right-hand side [second outer depletion gate] and the inner depletion gate [depletion gate on element 314 in the middle] and with a second helper gate [gate situated on element 310 between the second outer and inner depletion gates);
and wherein the first and second helper gates are each operable to connect electrically the channel region to respective leads (figure 3, paragraphs 0033-0035 where the first and second helper gates are operable [by nature of their gate function] and must connect to specific leads to have electrical connection to aid in the control of the channel region of which they are situated above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Hart et al to incorporate the teachings of Freedman et al in order to form a functioning qubit device with necessary gates to control the channel regions to form a memory device controlled by said gates.
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Figure 1: Figure 3 of Freedman et al (US 20180053809).
Regarding claims 18, 20, 23, and 25,
Hart et al as modified teaches all the limitations of the parent claim, claim 16, but does not specifically disclose
[claim 18] The semiconductor-superconductor hybrid device according to claim 16, wherein the first outer segment and the second outer segment each have lengths which are greater than or equal to a maximum superconducting coherence length of the semiconductor-superconductor hybrid device.
[claim 20] The semiconductor-superconductor hybrid device according to claim 16, wherein the elongate strip is unbranched.
[claim 23] The semiconductor-superconductor hybrid device according to claim 16, wherein the at least one inner depletion gate is a single depletion gate.
[claim 25] The semiconductor-superconductor hybrid device according to claim 16, wherein the first and second outer depletion gates are each pairs of opposed depletion gates.
However, Freedman et al further discloses
[claim 18] The semiconductor-superconductor hybrid device according to claim 16, wherein the first outer segment and the second outer segment each have lengths which are greater than or equal to a maximum superconducting coherence length of the semiconductor-superconductor hybrid device (figure 3, paragraph 0041, and figure 1 below where the first and second outer segments each have a length greater thant eh superconducting coherence length of the hybrid device, specifically each region has a length of at least one ‘L’ where L is defined as the coherence length of the superconducting material).
[claim 20] The semiconductor-superconductor hybrid device according to claim 16, wherein the elongate strip is unbranched (figure 3, paragraph 0035, where element 310 [super conducting elongated strip read onto from Harp et al] is unbranched [there are no branches present in each elongated strip]).
[claim 23] The semiconductor-superconductor hybrid device according to claim 16, wherein the at least one inner depletion gate is a single depletion gate (figure 3, paragraphs 0033-0035, where the inner depletion gate on the inner element 314 is a single depletion gate [there are no other depletion gates on said material or present]).
[claim 25] The semiconductor-superconductor hybrid device according to claim 16, wherein the first and second outer depletion gates are each pairs of opposed depletion gates (figure 3, paragraph 0033-0035 where the first and second outer depletion gates [as shown in figure 1 above] are a pair of depletion gates [they are not isolated but are on the same elongated strip and connected through the strip thus forming a pair]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Hart et al as modified to incorporate the teachings of Freedman et al to structure the superconducting heterostructure in such a way to maximize the efficiency of the device with lack of branching material and in one strip, minimizing the number of gates used to control the device, and keeping the superconducting material at such a length to allow for best usage.
Regarding claims 17, 19, and 27-30,
Hart et al further teaches
[claim 17] The semiconductor-superconductor hybrid device according to claim 16, wherein the outer depletion gates are configured to tune the outer segments to trivial regimes; and the at least one inner depletion gate is configured to tune the inner segment to a topological regime (as seen in the structure of the rejection of claim 16 above, all the structure is present in the combination of Hart et al. as modified, therefore without any clear difference in structure, the outer depletion gates could tune trivial regimes, while the inner depletion gate could be a topological regime).
[claim 19] The semiconductor-superconductor hybrid device according to claim 16, wherein both ends of the superconductor component are electrically grounded (figure 4, paragraph 0068, where each superconducting element is connected ot ehg ground plane).
[claim 27] The semiconductor-superconductor hybrid device according to claim 16, wherein the leads are regions of the semiconductor component (as seen in the rejection above to claim 16, the leads described in figure 3, paragraphs 0033-0035 where the first and second helper gates are operable [by nature of their gate function] and must connect to specific leads to have electrical connection to aid in the control of the channel region of which they are situated above would be part of the semiconductor region), the helper gates being configured to tune the leads to a normally-conductive state (as seen in the structure of the rejection of claim 16 above, all the structure is present in the combination of Hart et al. as modified, therefore without any clear difference in structure the helper gates could operate in this manner).
[claim 28] The semiconductor-superconductor hybrid device according to claim 16, wherein the leads are metal leads (figure 6, paragraph 0014, where the gate material are said to made of metal, and thus comprising a shape such as figure 6 where the leads [the portions sticking upward] are made of metal).
[claim 29] The semiconductor-superconductor hybrid device according to claim 16, wherein the leads extend perpendicular to the elongate strip (figure 6, paragraph 0014, where the gate material are said to made of metal, and thus comprising a shape such as figure 6 where the leads [the portions sticking upward] are perpendicular to the elongated strip of superconductor material [element 604]).
[claim 30] The semiconductor-superconductor hybrid device according to claim 16, wherein the semiconductor component is a heterostructure comprising a quantum well arranged between lower and upper barriers (figure 7, paragraph 0078, where the heterostructure comprises a quantum well [element 704] arranged between the upper [barrier 708] and lower [barrier 702] barriers).
[claim 31] The semiconductor-superconductor hybrid device according to claim 16, wherein the helper gates have respective tips configured to provide quantum point contacts between the channel region and the leads (as seen in the structure of the rejection of claim 16 above, all the structure is present in the combination of Hart et al. as modified, therefore without any clear difference in structure the helper gates and the top tip portion could operate in this manner).
Regarding claim 21,
Hart et al as modified teaches all the limitations of the parent claim, claim 16, but does not specifically disclose
[claim 21] The semiconductor-superconductor hybrid device according to claim 16, further comprising a dielectric arranged between the set of depletion gates and the superconductor component.
However, a different embodiment of Hart et al does teach
[claim 21] The semiconductor-superconductor hybrid device according to claim 16, further comprising a dielectric arranged between the set of depletion gates and the superconductor component (paragraph 0092, where the gate element [read onto each depletion gate from Freedman et al] comprises a dielectric [insulator] arranged between the superconducting component [element 808] and the gate component [element 812]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Hart et al as modified to incorporate the teachings of Hart et al to use a dielectric layer to protect and electrically isolate the metal gate material to allow for maximal efficiency of the device by minimizing any parasitic effects between metal material.
Allowable Subject Matter
Claims 22, 24, and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Abdo et al (US 20210280766), Lee et al (US 20210217946), Lutchyn et al (US 20210184094), Winkler et al (US 20210126181), Lampert et al (US 20200403137), Leipold et al (US 20200220065), and Hastings et al (US 20180052806) as superconductor heterostructures used for quantum computing with specific configurations.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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