Prosecution Insights
Last updated: July 17, 2026
Application No. 18/681,819

METHOD FOR REDUCING DAMAGE TO MAGNETIC TUNNEL JUNCTION OF MRAM

Final Rejection §112
Filed
Feb 06, 2024
Priority
Aug 20, 2021 — CN 202110962630.7 +1 more
Examiner
MCCALL SHEPARD, SONYA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Jiangsu Leuven Instruments Co. Ltd.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1097 granted / 1181 resolved
+24.9% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
42 currently pending
Career history
1205
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
73.5%
+33.5% vs TC avg
§102
16.8%
-23.2% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1181 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1, 11, 12 are objected to because of the following informalities: performing a first etching on a surface of the upper electrode facing away from the substrate until the lower electrode is exposed; and performing a second etching until the substrate is exposed, wherein ions incident on the sidewall of the MTJ layer in the second etching are scattered by the disarranged lattice structure in the first layer. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Regarding claims 1, 11 and 12, disarranging a lattice structure at a sidewall of the MTJ layer through etching to form a first layer with a preset thickness at the sidewall of the MTJ layer is not described in the specification in such a way as to enable one skilled in the art to which it pertains understand how to disarrange the lattice structure at the sidewall of the MTJ layer to form a first layer. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “disarranging a lattice structure at a sidewall of the MTJ layer through etching to form a first layer with a preset thickness at the sidewall of the MTJ layer; and performing second etching until the substrate is exposed, wherein ions incident on the sidewall of the MTJ layer in the second etching are scattered by the disarranged lattice structure in the first layer. The claim is indefinite for the following reasons: It is not clear what disarranging a lattice structure means. It is not clear if the etching step is a part of the first etching step or a separate step. Claims 2-10 are rejected under 112(a) first paragraph and 112(b) second paragraph because of their dependency on Claim 1. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Feb 06, 2024
Application Filed
Mar 27, 2026
Non-Final Rejection mailed — §112
Jun 08, 2026
Response Filed
Jun 30, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685177
RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME
2y 8m to grant Granted Jul 14, 2026
Patent 12672273
IMPLANT FOR TRANSISTOR BITLINE CONTACT AND JUNCTION FORMATION
2y 6m to grant Granted Jun 30, 2026
Patent 12666950
METAL ROUTING THAT OVERLAPS NMOS AND PMOS REGIONS OF A TRANSISTOR
4y 2m to grant Granted Jun 23, 2026
Patent 12666694
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
2y 12m to grant Granted Jun 23, 2026
Patent 12666949
CIRCUIT CELLS HAVING POWER STUBS
2y 12m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
97%
With Interview (+3.8%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1181 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month