Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 16-18, 21 and 23-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada et al. (Pub. No. US 2015/0171756 A1, herein Wada).
Regarding claim 1, Wada discloses a semiconductor system, comprising: a clamping circuit 17 (Fig. 6 and [0050]-[0052]), connected to a first terminal of a semiconductor device to prevent the semiconductor device from interference ([0057], [0066]); a first filter 14 ([0067]), connected to the clamping circuit (power supply circuit 31 in Fig. 6); a first operational amplifier (OP) 13, connected to the first filter 14, wherein the first OP is configured as a differential OP to generate a first output voltage ([0067]), so that a voltage drop across a measurement resistor is excluded and an on-state voltage drop across the semiconductor device is measured ([0035], [0123]); a second filter 14, connected to a second terminal of the semiconductor device; and a second OP 13, connected to the second filter (power supply 32 in Fig. 6 and [0075]), wherein the second OP is configured to generate a second output voltage so as to measure a current flowing through the semiconductor device (Figs. 6-7, 12-13, [0066]-[0068]), and the first output voltage and the second output voltage are configured to measure an on-resistance of the semiconductor device ([0125]).
Regarding claims 5 and 17, Wada discloses the semiconductor system of claim 1 or 16, wherein the clamping circuit comprises a clamping transistor (Fig. 6 and [0041]).
Regarding claim 16, Wada discloses a method for manufacturing and operating a semiconductor system, comprising: providing a clamping circuit 17 (Fig. 6 and [0050]-[0052]), connected to a first terminal of a semiconductor device for protecting the semiconductor device ([0057], [0066]); providing a first filter 14 ([0067]), connected to the clamping circuit (power supply circuit 31 in Fig. 6); providing a first operational amplifier (OP) 13, connected to the first filter 14 to generate a first output voltage ([0067]); providing a second filter 14, connected to a second terminal of the semiconductor device; providing a second OP 13, connected to the second filter to generate a second output voltage (power supply 32 in Fig. 6 and [0075]); and determining an on-resistance of the semiconductor device based on the first output voltage and the second output voltage (Figs. 6-7, 12-13, [0125]).
Regarding claim 18, Wada discloses the semiconductor system of claim 16, further comprising: turning on the clamping circuit after turning on the semiconductor device; and turning off the clamping circuit before turning off the semiconductor device (Fig. 6 and [0051]-[0054]).
Regarding claim 21, Wada discloses a semiconductor system, comprising: a clamping circuit 17 (Fig. 6 and [0050]-[0052]), connected to a first terminal of a semiconductor device ([0057], [0066]); a filter 14 ([0067]), connected to the clamping circuit (power supply circuit 31 in Fig. 6); an operational amplifier (OP) 13, connected to the filter 14, wherein the OP is configured to generate an output voltage; and a current sampling element, connected to a second terminal of the semiconductor device to measure the current passing through the semiconductor device (Figs. 6-7, 12-13, [0066]-[0068]), wherein the current and the output voltage are configured to evaluate an on-resistance of the semiconductor device ([0125]).
Regarding claim 23, Wada discloses the semiconductor system of claim 21, wherein the filter comprises: a first resistor R14, electrically connected to the clamping circuit 13; and a first capacitor C14, arranged in series with the first resistor and electrically connected to a ground (Fig. 3 and [0044]).
Regarding claim 24, Wada discloses the semiconductor system of claim 23, further comprising: a second resistor, arranged between a first terminal of the OP and the ground; and a third resistor, arranged between the first terminal of the OP and an output of the OP (An OP-AMP is typically composed of several internal circuit stages built from many transistors, current sources and resistors. An operational amplifier circuit inherently includes a first resister coupled between a first input terminal and ground, and a second resister coupled between the first input terminal and the output terminal of the operational amplifier.).
Regarding claim 25, Wada discloses the semiconductor system of claim 24, wherein a voltage gain of the OP corresponds to a resistance ratio of the third resistor to the second resistor, and the on-resistance of the semiconductor device is determined according to the output voltage, the voltage gain, and the current (Assuming an ideal non-inverting OP-AMP, the closed-loop voltage gain is Av = 1 + (Rf / Rg), where Rf is the feedback resistor between the output and the input node and Rg is the resistor between the input node and ground. The effective output resistance may be expressed as Rout = Vout / Iout, where Vout is the output voltage and Iout is the output current).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wada in view of Kawashima et al. (Pub. No. US 2023/0187529 A1, herein Kawashima).
Regarding claims 2 and 22, Wada does not specifically show the materials used for the semiconductor device.
However, in the same field of endeavor, Kawashima shows a semiconductor device, comprising: wherein the semiconductor device comprises: a substrate 200 ([0109]); a first nitride semiconductor layer 201 ([0110]) on the substrate; and a second nitride semiconductor layer 202 ([0112]) on the first nitride semiconductor layer, wherein a band gap of the second nitride semiconductor layer is greater than that of the first nitride semiconductor layer (Fig. 1A and [0003]) to provide a semiconductor device for power amplification capable of achieving both electric field relaxation by a source field plate and inhibiting the drain-source parasitic capacitance ([0009]-[0013]).
Therefore, given the teachings of Kawashima, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Wada in view of Kawashima by employing the III nitride semiconductor materials for the semiconductor system as they are known for the high breakdown voltages and excellent thermal stability.
Regarding claim 3, Wada in view of Kawashima teaches the semiconductor system of claim 2, wherein a drain electrode 205, a source electrode 204 and a gate electrode 206 of the semiconductor device are formed on the second nitride semiconductor layer (Fig. 1A and [0108]).
Regarding claim 4, Wada in view of Kawashima teaches the semiconductor system of claim 3, wherein the first terminal is connected with the drain electrode, and the second terminal is connected with the source electrode (Fig. 1A and [0108]).
Allowable Subject Matter
Claims 6-15 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claim 6, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a gate of the clamping transistor is electrically connected to a gate driver, and a drain electrode of the clamping transistor is electrically connected to the first terminal of the semiconductor device. Claims 7-15 are included likewise as they depend from claim 6.
With respect to claim 19, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, providing a second resistor, arranged between the first filter and a first terminal of the first OP; providing a third resistor, connected between the second filter and a second terminal of the first OP; providing a fourth resistor, arranged between a ground and the first terminal of the first OP; and evaluating a first voltage gain of the first OP by using a resistance ratio between the fourth resistor to the second resistor. Claim 20 is included likewise as it depends from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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June 23, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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