Prosecution Insights
Last updated: July 17, 2026
Application No. 18/681,866

SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Feb 07, 2024
Priority
Dec 13, 2022 — CN 202211594560.5 +1 more
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innoscience (Suzhou) Semiconductor Co. Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1043 granted / 1147 resolved
+22.9% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
1166
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
51.8%
+11.8% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1147 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group 1, claims 1-17 and 21-23, in the reply filed on April 27, 2026 is acknowledged. Accordingly, claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 27, 2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 7, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-7, 9, 10, 15, and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al (CN 114586176) (English equivalent Zhao et al (US Pub 2024/0047568)). In re claim 1, Zhao et al discloses a semiconductor apparatus, comprising: a first nitride semiconductor layer (i.e. 22); a second nitride semiconductor layer (i.e. 24) on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer (i.e. see at least paragraph 0042); an electrode (i.e. 30, 32, 26, or 28) contacting the second nitride semiconductor layer; a dielectric structure (i.e. 116, 118, 120, 130, 132) disposed on the second nitride semiconductor layer and covering the electrode; a field plate (i.e. 122, 123, 124, 125) in the dielectric structure; a plurality of height compensators (i.e. 134, 136, 138, 140, 144) in the dielectric structure and disposed on the electrode and the field plate, respectively; and a plurality of vias (i.e. 142) extending into the dielectric structure (i.e. 132) and contacting top surfaces of the plurality of height compensators (i.e. 144), respectively (i.e. see at least Figures 1-15L; paragraphs 0030-0127). In re claim 2, Zhao et al discloses wherein the top surfaces of the plurality of height compensators are coplanar (i.e. see at least Figure 3B). In re claim 3, Zhao et al discloses wherein the plurality of vias have a same length (i.e. see at least Figure 3B). In re claim 4, Zhao et al discloses wherein each of the plurality of height compensators comprises a lower via portion and an upper connecting portion above the lower via portion, and each of the plurality of vias contacts the upper connecting portion of a respective height compensator (i.e. see at least Figure 3B). In re claim 5, Zhao et al discloses wherein each of the plurality of vias is in misalignment with the lower via portion of the respective height compensator (i.e. see at least Figure 3B). In re claim 6, Zhao et al discloses wherein each of the plurality of vias is in alignment with the lower via portion of the respective height compensator (i.e. see at least Figure 3B). In re claim 7, Zhao et al discloses wherein the upper connecting portion of each of the plurality of height compensators has a width greater than that of a respective via (i.e. see at least Figure 3B). In re claim 9, Zhao et al discloses wherein for each of the plurality of height compensators, the upper connecting portion has a width greater than that of the lower via portion (i.e. see at least Figure 3B). In re claim 10, Zhao et al discloses wherein for each of the plurality of height compensators, the upper connecting portion is of a field plate structure (i.e. see at least Figure 3B). In re claim 15, Zhao et al discloses wherein the plurality of height compensators have different heights (i.e. see at least Figure 3B). In re claim 21, Zhao et al discloses a semiconductor apparatus, comprising: a first nitride semiconductor layer (i.e. 22); a second nitride semiconductor layer (i.e. 24) on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer (i.e. see at least paragraph 0042); a plurality of electrodes (i.e. 30, 32, 26, or 28) contacting the second nitride semiconductor layer; a dielectric structure (i.e. 116, 118, 120, 130, 132) disposed on the second nitride semiconductor layer and covering the plurality of electrodes; a field plate (i.e. 122, 123, 124, 125) in the dielectric structure; and a plurality of via structures (i.e. 142) extending into the dielectric structure and disposed on the plurality of electrodes, respectively, wherein each of the via structures comprises a via portion and a height-compensation portion disposed below the via portion (i.e. see at least Figures 1-15L; paragraphs 0030-0127). In re claim 22, Zhao et al discloses wherein the plurality of via structures are disposed on the plurality of electrodes and the field plate, respectively, and a height of the height-compensation portion of the via structure disposed on the field plate is different from heights of the height-compensation portions of the via structures disposed on the electrodes (i.e. see at least Figure 3B). In re claim 23, Zhao et al discloses wherein top surfaces of the height-compensation portions of the plurality of via structures are coplanar (i.e. see at least Figure 3B). Allowable Subject Matter Claims 8, 11-14, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Feb 07, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1147 resolved cases by this examiner. Grant probability derived from career allowance rate.

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