Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In the response to election filed on 05/13/2026, where applicant elected with traverse invention I which contains claims 1-7, 9-17, and 24. Additionally, upon reviewing the restriction, claim 19 in its current form is reconsidered and deemed to be a linking claim between invention I and invention II. Thus, claim 19 is examined upon the merits below. However, claims 20 and 21 contain matter that requires different text searches, and different classification searches which put unnecessary search burden on the examiner, therefore, remain withdrawn based on the original restriction. However, a rejoinder will be considered upon completion of prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9, 13-17, 19 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koezuke et al (US 20160225795).
Koezuke et al teaches
[claim 1] A metal oxide thin film transistor, comprising: a gate, a gate insulator layer, a metal oxide semiconductor layer, a source, a drain, and a first insulator layer that are successively stacked on a base substrate (figure 9A, paragraph 0073, where the thin film transistor [element 100] is made of a gate [element 104], a gate insulator [element 106], a metal oxide semiconductor layer [element 108], a source [element 112a], a drain [element 112b], and a first insulator layer [element 114] that are successively stacked on a base substrate [element 102]. Note per MPEP 2113 section I, a product by process claim is only examined by the resultant structure formed and not by any process steps that form said structure. The verbage “successively stacked” is a process, as “successively” being an adverb modifies the process by which the layers are stacked, the claim is only examined by the actual features in the claim – that is the presence of a gate, gate insulator, source, drain, metal oxide semiconductor layer, and an insulating layer);
wherein the first insulator layer is in contact with the metal oxide semiconductor layer (figure 9A, paragraph 0073, where element 114 [first insulator layer] is in contact with the metal oxide semiconductor layer [element 108]);
the first insulator layer is an inorganic insulator layer containing silicon and oxygen (figure 9A, paragraph 0127, where the first insulator layer [element 114] can be made of silicon oxide or silicon oxynitride which contains silicon and oxygen),
and an atomic percentage of oxygen contained in the first insulator layer is greater than 50% (figure 9A, paragraphs 0066 and 0127, where element 114 [first insulator layer] when made of silicon oxide is 2 parts oxygen and one part silicon, thus oxygen is more than 50% of the atomic percentage [specifically 66.67%]);
and an atomic percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45% (paragraph 0075, where element 108 can contain an oxide with Indium and Gallium where the chemical makeup is InGa2O3 where Oxygen has an atomic percentage of 50% which is greater than 45%).
[claim 2] The metal oxide thin film transistor according to claim 1, wherein a thickness of the first insulator layer is less than 2000 angstroms (paragraph 0127, where element 114 has a thickness less than 2000 angstroms, specifically 150nm which is 1500 angstroms which is less than 2000 angstroms).
[claim 3] The metal oxide thin film transistor according to claim 1, wherein a peak value of bond energy of a silicon-oxygen bond in the first insulator layer is greater than 1060 cm-1 and does not exceed 1080 cm-1 (paragraph 0127, where SiO2 has a known bond energy between 1000 cm-1 and 1100 cm-1 which contains an energy between 1060 cm-1 and 1080 cm-1).
[claim 4] The metal oxide thin film transistor according to claim 1, wherein the first insulator layer is a silicon oxide-based film layer formed by controlling an oxygen content during a deposition process, and differences between atomic percentages of oxygen at a plurality of test positions along a thickness direction of the first insulator layer do not exceed 5% (figure 9A, paragraph 0127 where element 114 is the first insulator layer and is a silicon-oxide layer [SiO2], where oxygen is bound to silicon throughout thus the differences of oxygen in a thickness direction is less than 5% [would be close to 0% in a typical silicon-oxide insulating layer]).
[claim 6] The metal oxide thin film transistor according to claim 1, further comprising: a second insulator film, disposed on a side, distal from the metal oxide semiconductor layer, of the first insulator layer, the second insulator film containing silicon and further containing at least one of oxygen and nitrogen (figure 9A, paragraphs 0073 and 0199, where element 116 is the second insulator film disposed on a side distal from the metal oxide semiconductor layer [element 108] of the first insulator layer [element 114] which contains oxygen and nitrogen [silicon oxynitride]).
[claim 7] The metal oxide thin film transistor according to claim 6, wherein the first insulator layer has an equal density at a plurality of test positions along a thickness direction; the density of the first insulator layer is less than a density of the second insulator film; and during etching of the first insulator layer using a hydrogen fluoride solution, an etch rate is greater than 25 angstoms/s and does not exceed 40 angstroms/s (paragraphs 0127, 0199 where the first insulating layer can be made of SiO2 and the second insulating layer can be made of SiN2O2 [silicon oxynitride], where the density of SiO2 [first insulator layer] is known to be less than the density of SiN2O2 [second insulator layer] at the same pressure [assumed to be atmospheric pressure]. Note, per MPEP 2113 section I, a process by product claim can only be examined upon the structure it creates and not the method used to produce said structure. Specifically the details regarding etch rate are not pertinent to the resultant structure but only the process of making the structure, thus only the language regarding the structure is examined.).
[claim 9] The metal oxide thin film transistor according to claim 6, wherein the second insulator film comprises a silicon nitride film layer (figure 9A, paragraph 0143, where element 116 can be a silicon nitride film layer).
[claim 13] The metal oxide thin film transistor according to claim 6, wherein a ratio of a thickness of the first insulator layer to a thickness of the second insulator film ranges from 0.2 to 0.5 (paragraphs 0127 and 0140 where the first insulator layer has a thickness ranging from 5 nm to 150nm, and the second insulator layer has a thickness ranging from 30 nm to 500 nm, where the ratio can be 0.3 [between 0.2 and 0.5] if the first is 150 nm and the second is 500 nm [150/500 = 0.3]).
[claim 14] The metal oxide thin film transistor according claim 1, wherein an atomic percentage of hydrogen contained in a silicon oxide film layer of the first insulator layer is less than 3%, and a percentage of silicon-hydrogen bonds in the silicon oxide film layer of the first insulator layer is less than 7% (figure 9A, paragraph 0127, where element 114 is the first insulator layer made of SiO2 which contains no hydrogen, thus the atomic percentage of hydrogen contained in the first insulator layer would be 0% which is less than 3%, and the silicon-hydrogen bonds would be less than 7% [0% < 7%]).
[claim 15] The metal oxide thin film transistor according to claim 1,wherein a thickness of the source and a thickness of the drain are greater than 3000 A and less than 6000 A, the thickness of the first insulator layer is greater than 500 A and does not exceed 1100 A, and a slope angle of the source and a slope angle of the drain are both less than 60 degrees (figure 9A, paragraph 0422, where elements 112a and 112b are the source and drain respectively, each has a thickness of 550 nm which is 5500 angstrom which is between 3000 and 6000 angstroms. Additionally, the slope of elements 112a and 112b with regards to the vertical plane is less than 60 degrees [confirmed visually]. Note: slope needs to be with reference to a specific plane).
[claim 16] The metal oxide thin film transistor according to claim 1, wherein the metal oxide semiconductor layer comprises a first surface and a second surface that are opposite to each other, the first surface being closer to the base substrate (figure 9A, paragraphs 0074-0077, where element 108 is the metal oxide semiconductor and comprises a first surface [bottom surface of element 108/108a], and a second surface [top surface of element 108/108b], where the surfaces are opposite of each other, and the first surface is closer to the substrate);
and a portion, proximal to the first surface, of the metal oxide semiconductor layer contains amorphous or nano-crystalline metal oxide (figure 9A, paragraph 0112, where element 108a [part of element 108, contains the first surface] can be amorphous metal oxide),
and a portion, proximal to the second surface, of the metal oxide semiconductor layer contains C-axis crystallized metal oxide (figure 9A, paragraph 0112, where element 108b [part of element 108, contains the second surface] can be a metal oxide semiconductor which is a C-axis crystallized metal oxide);
wherein the amorphous or nano-crystalline metal oxide contains at least one of indium, gallium, zinc, tin, and praseodymium; and the C-axis crystallized metal oxide containing at least one of indium, gallium, zinc, tin, and praseodymium (figure 9A, paragraphs 0075-0077, where elements 108a and 108b both contain indium and zinc).
[claim 17] The metal oxide thin film transistor according to claim 16, wherein the amorphous or nano-crystalline metal oxide contains indium gallium zinc oxide, an atomic ratio of indium to gallium to zinc in the indium gallium zinc oxide being 4:2:3, 1:1:1, or 1:3:6 (figure 9A, paragraphs 0075-0077, where element 108a can be made of Indium, Gallium, and a zinc oxide where the atomic ration can be 4:2:3 [i.e. In:Ga:Zn=4]);
and the C-axis crystallized metal oxide contains indium gallium zinc oxide, an atomic ratio of indium to gallium to zinc in the indium gallium zinc oxide being 4:2:3, 1:1:1, or 1:3:6 (figure 9B, paragraphs 0075-0077, where element 108b [c-axis crystallized metal oxide] contains an indium, gallium, zinc oxide and has an atomic ration of 1:1:1 [i.e. In:Ga:Zn = 1]).
[claim 19] A method for manufacturing a metal oxide thin film transistor, comprising: forming a gate, a gate insulator layer, a metal oxide semiconductor layer, a source, a drain, and a first insulator layer that are successively stacked on a base substrate (figure 9A, paragraph 0073, where the thin film transistor [element 100] is made of a gate [element 104], a gate insulator [element 106], a metal oxide semiconductor layer [element 108], a source [element 112a], a drain [element 112b], and a first insulator layer [element 114] that are successively stacked on a base substrate [element 102]. Note per MPEP 2113 section I, a product by process claim is only examined by the resultant structure formed and not by any process steps that form said structure. The verbage “successively stacked” is a process, as “successively” being an adverb modifies the process by which the layers are stacked, the claim is only examined by the actual features in the claim – that is the presence of a gate, gate insulator, source, drain, metal oxide semiconductor layer, and an insulating layer);
wherein the first insulator layer is in contact with the metal oxide semiconductor layer (figure 9A, paragraph 0073, where element 114 [first insulator layer] is in contact with the metal oxide semiconductor layer [element 108]);
the first insulator layer is an inorganic insulator layer containing silicon and oxygen (figure 9A, paragraph 0127, where the first insulator layer [element 114] can be made of silicon oxide or silicon oxynitride which contains silicon and oxygen),
and an atomic percentage of oxygen contained in the first insulator layer is greater than 50% (figure 9A, paragraphs 0066 and 0127, where element 114 [first insulator layer] when made of silicon oxide is 2 parts oxygen and one part silicon, thus oxygen is more than 50% of the atomic percentage [specifically 66.67%]);
and an atomic percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45% (paragraph 0075, where element 108 can contain an oxide with Indium and Gallium where the chemical makeup is InGa2O3 where Oxygen has an atomic percentage of 50% which is greater than 45%).
[claim 24] A display panel, comprising: a base substrate, and a plurality of metal oxide thin film transistors disposed on the base substrate (figures 18 and 19, paragraph 0309, where element 701 is the substrate and a plurality metal oxide thin film transistors are disposed over the substrate [seen by elements 750 and 752, and by figures 21A-21C where each display pixel has a transistor);
A metal oxide thin film transistor, comprising: a gate, a gate insulator layer, a metal oxide semiconductor layer, a source, a drain, and a first insulator layer that are successively stacked on a base substrate (figure 9A, paragraph 0073, where the thin film transistor [element 100] is made of a gate [element 104], a gate insulator [element 106], a metal oxide semiconductor layer [element 108], a source [element 112a], a drain [element 112b], and a first insulator layer [element 114] that are successively stacked on a base substrate [element 102]. Note per MPEP 2113 section I, a product by process claim is only examined by the resultant structure formed and not by any process steps that form said structure. The verbage “successively stacked” is a process, as “successively” being an adverb modifies the process by which the layers are stacked, the claim is only examined by the actual features in the claim – that is the presence of a gate, gate insulator, source, drain, metal oxide semiconductor layer, and an insulating layer);
wherein the first insulator layer is in contact with the metal oxide semiconductor layer (figure 9A, paragraph 0073, where element 114 [first insulator layer] is in contact with the metal oxide semiconductor layer [element 108]);
the first insulator layer is an inorganic insulator layer containing silicon and oxygen (figure 9A, paragraph 0127, where the first insulator layer [element 114] can be made of silicon oxide or silicon oxynitride which contains silicon and oxygen),
and an atomic percentage of oxygen contained in the first insulator layer is greater than 50% (figure 9A, paragraphs 0066 and 0127, where element 114 [first insulator layer] when made of silicon oxide is 2 parts oxygen and one part silicon, thus oxygen is more than 50% of the atomic percentage [specifically 66.67%]);
and an atomic percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45% (paragraph 0075, where element 108 can contain an oxide with Indium and Gallium where the chemical makeup is InGa2O3 where Oxygen has an atomic percentage of 50% which is greater than 45%).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koezuke et al (US 20160225795) in view of Yamazaki et al (US 201501249160).
Koezuke et al teaches all of the limitations of the parent claim, claims 1, but does not specifically disclose
[claim 5] The metal oxide thin film transistor according to claim 1, wherein the first insulator layer comprises a first surface and a second surface that are opposite to each other, wherein the first surface is a surface proximal to the metal oxide semiconductor layer, and the second surface is a surface distal from the metal oxide semiconductor layer; and in a plurality of test positions tested from the second surface to the first surface, the closer the test position is to the second surface, the greater is a difference between atomic percentages of oxygen contained at every adjacent two test positions, and the closer the test position is to the first surface, the smaller is the difference between the atomic percentages of oxygen contained at every adjacent two test positions.
However, Yamazaki et al does teach
[claim 5] The metal oxide thin film transistor according to claim 1, wherein the first insulator layer comprises a first surface and a second surface that are opposite to each other, wherein the first surface is a surface proximal to the metal oxide semiconductor layer, and the second surface is a surface distal from the metal oxide semiconductor layer (figure 1B, paragraphs 0085, where element 114 and 116 comprise the first insulating layer, and the first surface is a bottom surface of the insulating layer and the top surface is the second surface of the insulating layer which are opposite to one another);
and in a plurality of test positions tested from the second surface to the first surface, the closer the test position is to the second surface, the greater is a difference between atomic percentages of oxygen contained at every adjacent two test positions, and the closer the test position is to the first surface, the smaller is the difference between the atomic percentages of oxygen contained at every adjacent two test positions (figure 1B, paragraphs 0086-0087, where oxygen is injected into the insulating layer [114 and 116] and then moves towards the metal oxide semiconductor layer [element 108] such that the oxygen is released from elements 114 and 116 into the oxide semiconductor layer. In such a case, oxygen moves down towards element 108, such that two test points near the top layer [second layer] may have a more dispersed oxygen content than the portion near the oxide semiconductor layer, such that two test portions near the first surface will have a less dispersed oxygen content, such that the atomic percentage of two test positions closer to the first surface will have a smaller difference than the atomic percentage difference between two test points near the second [top] surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Koezuke et al with the teachings of Yamazaki et al to incorporate more oxygen rich insulating layer to allow for oxygen to drift into the semiconductor layer to create a more insulative insulation layer to allow for better electrical connection within the transistor.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koezuke et al (US 20160225795) in view of Yamazaki et al (US 20110101335).
Koezuke et al teaches all of the limitations of the parent claim, claim 6, but does not specifically disclose
[claim 10] The metal oxide thin film transistor according to claim 6, wherein the second insulator film comprises a silicon oxide film layer and a silicon nitride film layer that are successively stacked on the first insulator layer; wherein an atomic percentage of oxygen in the silicon oxide film layer of the second insulator film does not exceed an atomic percentage of oxygen in a silicon oxide film layer of the first insulator layer, and a difference between the atomic percentage of oxygen in the silicon oxide film layer of the second insulator film and the atomic percentage of oxygen in the silicon oxide film layer of the first insulator layer is greater than 5% to 15%.
However, Yamazaki et al teaches
[claim 10] The metal oxide thin film transistor according to claim 6, wherein the second insulator film comprises a silicon oxide film layer and a silicon nitride film layer that are successively stacked on the first insulator layer (figure 7, paragraphs 0400 and 0411, where element 386 and 373 comprise the second insulator film and is made up of silicon oxide [element 386] and silicon nitride [element 373]);
wherein an atomic percentage of oxygen in the silicon oxide film layer of the second insulator film does not exceed an atomic percentage of oxygen in a silicon oxide film layer of the first insulator layer, and a difference between the atomic percentage of oxygen in the silicon oxide film layer of the second insulator film and the atomic percentage of oxygen in the silicon oxide film layer of the first insulator layer is greater than 5% to 15% (figure 7, paragraph 0397, where element 389 is the first insulating layer and is oxygen rich, more than a standard silicon oxide film. Thus the second insulating layer cannot have a greater atomic percentage of oxygen over element 389 [first insulating layer], likewise the amount by which element 389 has a greater atomic percentage of oxygen dependent upon SiO.sub.2+x, where the value of x can range from 0 to 3, where if it were 3 is more than 15% greater atomic percentage of oxygen).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Koezuke et al with the teachings of Yamazaki et al to incorporate more oxygen rich insulating layer to allow for oxygen to drift into the semiconductor layer to create a more insulative insulation layer to allow for better electrical connection within the transistor.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koezuke et al (US 20160225795) in view of Yamazaki et al (US 20150249160) and Yamazaki et al (US 20110101335).
Regarding claim 11,
Koezuke et al teaches all of the limitations of the parent claim, claim 6, but does not specifically disclose
[claim 11] The metal oxide thin film transistor according to claim 6, wherein the second insulator film comprises a silicon oxide film layer, a silicon oxynitride film layer, and a silicon nitride film layer that are successively stacked on the first insulator layer; wherein an atomic percentage of oxygen in the silicon oxide film layer of the second insulator film does not exceed an atomic percentage of oxygen in a silicon oxide film layer of the first insulator layer, a difference between the atomic percentage of oxygen in the silicon oxide film layer of the second insulator film and the atomic percentage of oxygen in the silicon oxide film layer of the first insulator layer is greater than 5% to 15%.
However, Yamazaki et al (160) teaches
[claim 11] The metal oxide thin film transistor according to claim 6, wherein the second insulator film comprises a silicon oxide film layer, a silicon oxynitride film layer, and a silicon nitride film layer that are successively stacked on the first insulator layer (figure 1B, paragraphs 0085, 0130, and 0146, where element 113a/b is the first insulating layer, and elements 114, 116 and 118 comprise the second insulating layer. Where elements 114, 116 and 118 are made of silicon oxide, silicon oxynitride and silicon nitride, respectively, and stacked successively upon the first insulating layer [element 113a/b]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Koezuke et al to incorporate the teachings of Yamazaki et al to incorporate a silicon oxide, silicon oxynitride and silicon nitride layer over the conductors and semiconductor layer to provide a more efficient insulating layer to allow for better electrical connection within the transistor and thus better performance.
Additionally, Koezuke et al as modified does not specifically disclose
[claim 11] wherein an atomic percentage of oxygen in the silicon oxide film layer of the second insulator film does not exceed an atomic percentage of oxygen in a silicon oxide film layer of the first insulator layer, a difference between the atomic percentage of oxygen in the silicon oxide film layer of the second insulator film and the atomic percentage of oxygen in the silicon oxide film layer of the first insulator layer is greater than 5% to 15%.
However, Yamazaki et al (335) teaches
[claim 11] wherein an atomic percentage of oxygen in the silicon oxide film layer of the second insulator film does not exceed an atomic percentage of oxygen in a silicon oxide film layer of the first insulator layer, a difference between the atomic percentage of oxygen in the silicon oxide film layer of the second insulator film and the atomic percentage of oxygen in the silicon oxide film layer of the first insulator layer is greater than 5% to 15% (figure 7, paragraph 0397, where element 389 is the first insulating layer and is oxygen rich, more than a standard silicon oxide film. Thus the second insulating layer cannot have a greater atomic percentage of oxygen over element 389 [first insulating layer], likewise the amount by which element 389 has a greater atomic percentage of oxygen dependent upon SiO.sub.2+x, where the value of x can range from 0 to 3, where if it were 3 is more than 15% greater atomic percentage of oxygen).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Koezuke et al as modified with the teachings of Yamazaki et al (335) to incorporate more oxygen rich insulating layer to allow for oxygen to drift into the semiconductor layer to create a more insulative insulation layer to allow for better electrical connection within the transistor.
Regarding claim 12,
Koezuke et al as modified teaches all of the limitations of the parent claim, claim 11, but does not specifically disclose
[claim 12] The metal oxide thin film transistor according to claim 11, wherein an atomic ratio of silicon to oxygen in the silicon oxide film layer is 33:67, an atomic ratio of silicon to oxygen to nitrogen in the silicon oxynitride film layer is 36:52:12, and an atomic ratio of silicon to nitrogen in the silicon nitride film layer is 51:49.
However, according to MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts, and Proportions [R-01.2024]
II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Koezuke et al as modified to use different variations of a silicon oxide, silicon oxynitride and silicon nitride layer to optimize the function of the device. In particular, a silicon oxide layer has a base atomic percentage of 33:67 percent silicon to oxygen, a silicon oxynitride layer has a base atomic percentage of 40:40:10% silicon to nitrogen to oxygen and silicon nitride has a base atomic percentage of 43:57% silicon to nitrogen. Each one of these layers can be enriched with oxygen, silicon or nitrogen to change the atomic percentage depending on a use case (more nitrogen means less oxygenation which means less oxidation of metal layers). Depending on the specific use case and need for reliability, one of ordinary skill in the art could adjust percentages accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sakama et al (US 20010011725), Yamazaki et al (US 20110114999), Jung et al (US 20110127518), Koezuka et al (US 20140110707), and Okazaki et al (US 20150372022) as thin film transistors with specific properties similar to those claims, such as silicon oxide, silicon oxnitride, and silicon nitride insulating layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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