DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 9 February 2024. In view of this communication, claims 1-9 and 11-21 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 9, 11-16, and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaidi et al. (JP 2020180366 A), hereinafter referred to as Kaidi et al., in view of Kondo (JP 2003218500 A), hereinafter referred to as Kondo.
Regarding claim 1, Kaidi et al. teaches a metal foil, comprising a conductive layer (3) and a bearing layer (1, 2, 4), the conductive layer (3) and the bearing layer (1, 2, 4) being stacked (Fig. 2; page 3, paragraph 3: carrier layer 1, release layer 2, and ultrathin copper layer 3 are stacked; page 5, paragraph 3: transition layer 4 between copper layer 3 and release layer 2), wherein the conductive layer (3) is configured to manufacture a conductive line (page 6, final paragraph: copper layer 3 is etched to form a circuit); and a roughness Rz of a surface, close to the conductive layer (3), of the bearing layer (1, 2, 4) is less than or equal to 2 microns (page 3, paragraph 7: the roughness of the carrier layer is 1.5 microns or less).
Kaidi et al. does not teach that when a circuit board is manufactured using the metal foil, the bearing layer (1, 2, 4) is separated from the conductive layer (3) by a first etching solution; the conductive layer has a corrosion resistance to the first etching solution. Kondo does teach that when a circuit board is manufactured using the metal foil, the bearing layer (11) is separated from the conductive layer (22) by a first etching solution; the conductive layer (22) has a corrosion resistance to the first etching solution (Kondo page 7, paragraph 10: in the process of putting the copper foil on a circuit board, the support member 11 is etched while the copper pattern 22 is not).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the carrier of Kaidi et al. from nickel as taught by Kondo such that the etching solution used on the nickel carrier does not etch the copper conductive layer. Kondo teaches that this method of etching enables manufacturing a board without positional deviations or changes to the size or shape of the copper foil (Kondo page 7, paragraph 11).
Regarding claim 2, Kaidi et al. teaches the metal foil according to claim 1, wherein the roughness Rz of the surface, close to the conductive layer (3), of the bearing layer (1, 2, 4) is less than or equal to 1 micron (page 3, paragraph 7: the roughness of the carrier layer is 1.5 microns or less).
Regarding claim 3, Kaidi et al. teaches the metal foil according to claim 1, wherein the bearing layer comprises a transition layer (4), the transition layer (4) and the conductive layer (3) being stacked.
Kaidi et al. does not teach that when the circuit board is manufactured using the metal foil, the transition layer (4) is etched by the first etching solution, so that the bearing layer is separated from the conductive layer. Kondo does teach that when the circuit board is manufactured using the metal foil, the transition layer is etched by the first etching solution, so that the bearing layer is separated from the conductive layer (Kondo page 7, paragraph 10: in the process of putting the copper foil on a circuit board, the support member 11 is etched while the copper pattern 22 is not).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch away the transition layer of Kaidi et al. as taught by Kondo because Kondo teaches that etching enables manufacturing a board without positional deviations or changes to the size or shape of the copper foil (Kondo page 7, paragraph 11).
Regarding claim 4, Kaidi et al. teaches the transition layer has a corrosion resistance to a second etching solution, wherein the second etching solution is an etching solution capable of etching the conductive layer (since the transition layer of Kaidi et al. is a nickel allow layer and the conductive layer is a copper layer (see rejection of claim 5, below), it is inherent that different etching solutions will have to be used for each layer).
Regarding claim 5, Kaidi et al. teaches the metal foil according to claim 4, wherein the conductive layer (3) is a copper layer (page 3, paragraph 3: layer 3 is a copper layer), and the transition layer (4) contains at least one of nickel, chromium, manganese, iron and cobalt elements (page 5, paragraph 3: metal layer 4 is a nickel alloy layer).
Regarding claim 6, Kaidi et al. teaches the metal foil according to claim 1, wherein a thickness of the bearing layer (1, 2, 4) is 8 microns to 105 microns (page 3, paragraph 8: the thickness of the carrier layer 1 is between 12 to 35 microns; page 4, paragraph 4: the layer 2 is between 5 and 50 nm thick; page 5, paragraph 3: metal layer 4 is 5 to 10 nm thick).
Regarding claim 7, Kaidi et al. teaches the metal foil according to claim 3, wherein the bearing layer (1, 2, 4) further comprises a carrier layer (1), the transition layer (4) being arranged between the carrier layer (1) and the conductive layer (3) (Fig. 2; page 3, paragraph 3: carrier layer 1, release layer 2, and ultrathin copper layer 3 are stacked; page 5, paragraph 3: transition layer 4 between copper layer 3 and release layer 2, which is stacked on top of carrier layer 1).
Regarding claim 9, Kaidi et al. teaches the metal foil according to claim 7, wherein when the circuit board is manufactured using the metal foil, the carrier layer (1) is removed in a non-peel-off manner; or wherein when the circuit board is manufactured using the metal foil, the carrier layer (1) is removed in a peel-off manner (page 5, final paragraph: the carrier layer is removed when the foil is used in the manufacture of a circuit board).
Regarding claim 11, Kaidi et al. teaches the metal foil according to claim 7, wherein a material of the transition layer (4) has a corrosion resistance to a third etching solution, wherein when the circuit board is manufactured using the metal foil, the carrier layer (1) is etched by the third etching solution (Kaidi et al. page 3, paragraph 6 and page 5, paragraph 3: the carrier layer 1 is copper and the transition layer 4 is a nickel alloy, which each require different etching solutions).
Regarding claim 12, Kaidi et al. teaches the metal foil according to claim 7, wherein the bearing layer (1, 2, 4) further comprises a release layer (2), the release layer (2) being arranged between the carrier layer (1) and the transition layer (4) (Fig. 2; page 3, paragraph 3: carrier layer 1, release layer 2, and ultrathin copper layer 3 are stacked).
Regarding claim 13, Kaidi et al. teaches the metal foil according to claim 7, wherein a sum of the thicknesses of the conductive layer (3) and the transition layer (4) is greater than or equal to 0.2 microns (page 4, second-to-last paragraph: copper layer 3 is between 0.5 and 10 microns thick).
Regarding claim 14, Kaidi et al. teaches a circuit board, wherein the circuit board is manufactured using a substrate (page 5, last paragraph: wiring board comprising a resin substrate) and the metal foil according to claim 1 (see rejection of claim 1, above).
Regarding claim 15, Kaidi et al. teaches a method for manufacturing a circuit board, wherein the circuit board is manufactured using the metal foil according claim 1, and the method for manufacturing the circuit board comprises:
performing circuit manufacturing on the conductive layer (3) to obtain a conductive line (page 5, last paragraph: the ultrathin copper layer 3 is etched to form a circuit);
combining the conductive line (3) with a substrate (page 5, last paragraph: laminating the ultrathin copper layer 3 with a resin layer); and
removing the bearing layer (1, 2, 4) (page 5, last paragraph: the carrier layer 1 and the peeling layer 2 are removed).
Regarding claim 16, Kaidi et al. teaches the method for manufacturing the circuit board according to claim 15, wherein after removing the bearing layer, the method further comprises:
performing a surface treatment on the conductive line, so that a height difference between a surface of the conductive line and a surface of the substrate is within a preset height difference range (page 5, last paragraph: copper layer 3 is etched and conforms to the height stated on page 4, second-to-last paragraph of 0.5 to 10 microns).
Regarding claim 20, Kaidi et al. teaches a multilayer circuit board, comprising the circuit board according to claim 14 and/or the circuit board manufactured by the a method for manufacturing the circuit board, wherein the circuit board is manufactured using the metal foil, and the method for manufacturing the circuit board comprises:
performing circuit manufacturing on the conductive layer (3) to obtain a conductive line (page 5, last paragraph: the ultrathin copper layer 3 is etched to form a circuit);
combining the conductive line with a substrate (page 5, last paragraph: laminating the ultrathin copper layer 3 with a resin layer); and
removing the bearing layer (1, 2, 4) (page 5, last paragraph: the carrier layer 1 and the peeling layer 2 are removed).
Regarding claim 21, Kaidi et al. teaches a method for manufacturing a multilayer circuit board (page 5, last paragraph), comprising the method for manufacturing the circuit board according to claim 15 (see rejection of claim 15 above).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaidi et al. in view of Kondo, in further view of Jia et al. (CN 113646469 A), hereinafter referred to as Jia et al.
Regarding claim 8, Kaidi et al. in view of Kondo teaches the metal foil according to claim 7, but does not teach that the material of the carrier layer is selected from at least one of metal and non-metal.
Jia et al. does teach that the material of the carrier layer is selected from at least one of metal and non-metal (page 11, paragraph 4: carrier 17 may be a resin film coated with a metal material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the carrier layer of Kaidi et al. in view of Kondo from a copper-coated resin material as taught by Jia et al. because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416."
Allowable Subject Matter
Claims 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim performing film pasting, exposure and development operations on the conductive layer to obtain a masking pattern, wherein an area, not masked by the masking pattern, of the conductive layer is a non-conductive line area; etching the non-conductive line area using a second etching solution; and removing the masking pattern to obtain the conductive line.
Regarding claim 18, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited, performing film pasting, exposure and development operations on the conductive layer to obtain a masking pattern, wherein an area, not masked by the masking pattern, of the conductive layer is a conductive line area; thickening the conductive line area; removing the masking pattern; and Preliminary Amendment performing rapid etching using the second etching solution to remove a non-thickened area of the conductive layer to obtain the conductive line.
Conclusion
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847