DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-2, 5-6, 8, 10-17, and 19-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, 8, 10, 15-17, 20-21, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Zaman et al. (US Pub.: 2020/0328192) in view of MUSLEH et al. (US Pub.: 2021/0092069), and Atsatt et al. (US Pub.: 2019/0041923).
As per claim 1, Zaman teaches/suggests a computing system comprising: a plurality of functional blocks (e.g. associated Fig. 7, ref. 500), wherein each of the plurality of functional blocks is an instance of a computing circuitry block, and wherein a first functional block of the plurality of functional block is configure to: operating with the plurality of functional blocks; and operating accordingly of the first functional block (Fig. 7; [0046]-[0048]); and a globals block (e.g. associated with Fig. 5, ref. 502, 504-1, 504-2, 506+510, 508-1, 508-2) having a same footprint as an individual one of the functional blocks, the globals block comprising circuitry that is different than the functional block, wherein the plurality of functional blocks and the globals block are included in an array, wherein the globals block is surrounded by functional blocks of the plurality of functional blocks in the array, and wherein the globals block and each of the functional blocks operate accordingly (Fig. 7; [0046]-[0048]), and wherein the globals block operating accordingly with the first functional block and additional functional blocks of the plurality of functional blocks (Fig. 5-7; [0014]-[0026]; and [0033]-[0048]).
Zaman does not expressly teach the computing system comprise:
receive telemetry output indicative of one or more sensor readings associated with block; and
determine, based on the telemetry output, to adjust one or more operating parameters of block; and
an instance of a same input/output (I/O) interface and communications circuitry, and provides the telemetry output.
MUSLEH teaches/suggests a computing system comprising: an instance of a same input/output (I/O) interface and communications circuitry (e.g. associated with circuitry being able to interchangeable, suggesting the each interchangeable circuitry having the instance of the same I/O interface and communication circuitry: [0182]-[0183]) ([0169]-[0183]; and [0286]).
Atsatt teaches/suggests a computing system comprising: receive telemetry output (e.g. associated with receiving signaling for adjusting operations of voltage regulator: [0023]-[0024]) indicative of one or more sensor readings associated with block (e.g. associated with monitor/measuring temperature: [0023]-[0024]); and determine, based on the telemetry output, to adjust one or more operating parameters of block (e.g. associated with adjusting the operation of voltage regulator: [0023]-[0024]); and provides the telemetry output (e.g. associated with providing signaling for adjusting operations of voltage regulator: [0023]-[0024]) ([0022]-[0025]; and [0046]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include MUSLEH’s interchangeable architecture, and Atsatt’s voltage regulating architecture into Zaman’s computing system for the benefit of enabling an hybrid design that can mix and match different technology (MUSLEH, [0183]), and improving power management capabilities (Atsatt, [0025]) to obtain the invention as specified in claim 1.
As per claim 2, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the array comprises a plurality of globals blocks, and the globals blocks comprise the globals block (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0048]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 5, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 2 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the globals blocks are fewer than 5% of a total number of the functional and globals blocks of the array (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0111]; [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]), wherein it would have been obvious design choice to one of ordinary skilled in the art to design the custom integrated circuit to have global block being fewer than 5% of total all blocks.
As per claim 6, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the globals block comprises a sensor configured to sense at least one of temperature or voltage, and the one or more sensor reading comprising a reading from the sensor (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 8, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the globals block is configured to provide an interrupt to at least one of the plurality of functional blocks (Zaman, [0058]) (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 10, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the globals block is electrically connected to at least two of the plurality of functional blocks (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 15, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the globals block comprises non-volatile memory (Zaman, [0021]; [0036]) (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 16, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the globals block comprises input/output circuitry, and the input/output circuitry 1s configured to communicate with circuitry that is outside the array (Zaman, [0035]-[0036]) (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 17, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein each of the functional blocks of the plurality of functional blocks comprises an interface along each edge and computing circuitry, and wherein each of the plurality of functional blocks is electrically connected to at least two adjacent functional blocks of the plurality of functional blocks (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]), wherein it would have been an obvious design choice for one of ordinary skilled in the art to rearrangement the blocks to further implement the above claimed features.
As per claim 20, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the computing system comprising wherein the computing system is configured to perform neural network training (Zaman, [0192]-[0198]) (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0192]-[0198]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 21, Zaman teaches/suggests a method of operating a computing system, the method comprising: measuring, by a globals block (e.g. associated with Fig. 5, ref. 502, 504-1, 504-2, 506+510, 508-1, 508-2), a parameter (e.g. associated with measuring/decrypting of packet: Fig. 7; [0046]-[0048]; [0052]); generating, by the globals block, a signal based on the parameter (e.g. associated with decrypted data/signal being generated accordingly: Fig. 7; [0046]-[0048]; [0052]), operating in association with a plurality of functional blocks; and operating, by the globals block, in association with a functional block of the plurality of functional blocks (e.g. associated Fig. 7, ref. 500) (Fig. 7; [0046]-[0048]; and [0052]), operating, by the functional block, operations of the functional block, wherein the globals block and the plurality of functional blocks are in an array, wherein the globals block comprises circuitry that is different than the functional block, and wherein each of the globals block and the functional block operate accordingly (Fig. 7; [0046]-[0048]), wherein the signal comprises data associated with the plurality of functional blocks and operates in association with the plurality of functional blocks (Fig. 5-7; [0014]-[0026]; [0033]-[0048]; and [0051]-[0052]).
Zaman does not expressly teach the computing system comprising:
wherein the signal comprises telemetry output indicative of one or more sensor readings associated with block;
providing, by a first block, the signal to a second block; and
determining, based on the telemetry output, to adjust one or more operating parameters of block,
comprises an instance of a same input/output (I/O) interface and communications circuitry.
MUSLEH teaches/suggests a method comprising: providing, by a first block, the signal to a second block, and comprises an instance of a same input/output (I/O) interface and communications circuitry (e.g. associated with circuitry being able to interchangeable, suggesting the each interchangeable circuitry having the instance of the same I/O interface and communication circuitry: [0182]-[0183]) ([0169]-[0183]; and [0286]).
Atsatt teaches/suggests a method comprising: wherein the signal comprises telemetry output (e.g. associated with receiving signaling for adjusting operations of voltage regulator: [0023]-[0024]) indicative of one or more sensor readings associated with block (e.g. associated with monitor/measuring temperature: [0023]-[0024]); and determining, based on the telemetry output, to adjust one or more operating parameters of block (e.g. associated with adjusting the operation of voltage regulator: [0023]-[0024]) ([0022]-[0025]; and [0046]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include MUSLEH’s interchangeable architecture, and Atsatt’s voltage regulating architecture into Zaman’s computing system for the benefit of enabling an hybrid design that can mix and match different technology (MUSLEH, [0183]), and improving power management capabilities (Atsatt, [0025]) to obtain the invention as specified in claim 21.
As per claim 24, Zaman, MUSLEH, and Atsatt teach/suggest all the claimed features of claim 21 above, where Zaman, MUSLEH, and Atsatt further teach/suggest the method further comprising providing the signal to a second functional block of the plurality of functional blocks (Zaman, [0192]-[0198]) (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0192]-[0198]; [0286]; and Atsatt, [0022]-[0025]; [0046]).
As per claim 25, Zaman teaches/suggests a computing system comprising: a plurality of functional blocks (e.g. associated Fig. 7, ref. 500), wherein each of the plurality of functionals blocks comprises an instance of a computing circuitry element, and wherein a first functional block of the plurality of functional block is configure to: operating with the plurality of functional blocks; and operating accordingly of the first functional block (Fig. 7; [0046]-[0048]); and a globals block (e.g. associated with Fig. 5, ref. 502, 504-1, 504-2, 506+510, 508-1, 508-2) having a same footprint as an individual one of the functional blocks, the globals block comprising circuitry that is different than the functional block, wherein the plurality of functional blocks and the globals block are included in an array, wherein each of the globals block and the individual one of the functional block operate accordingly (Fig. 7; [0046]-[0048]), wherein the globals block operating accordingly with the first functional block and additional functional blocks of the plurality of functional blocks (Fig. 5-7; [0014]-[0026]; [0033]-[0048]; and [0051]-[0052]).
Zaman does not expressly teach the computing system comprises:
receive telemetry output indicative of one or more sensor readings associated with block;
determine, based on the telemetry output, to adjust one or more operating parameters of block; and
an instance of a same input/output (I/O) interface and communications circuitry, provides the telemetry output.
MUSLEH teaches/suggests a computing system comprising an instance of a same input/output (I/O) interface and communications circuitry (e.g. associated with circuitry being able to interchangeable, suggesting the each interchangeable circuitry having the instance of the same I/O interface and communication circuitry: [0182]-[0183]) ([0169]-[0183]; and [0286]) .
Atsatt teaches/suggests a computing system comprising: receive telemetry output (e.g. associated with receiving signaling for adjusting operations of voltage regulator: [0023]-[0024]) indicative of one or more sensor readings associated with block (e.g. associated with monitor/measuring temperature: [0023]-[0024]); determine, based on the telemetry output, to adjust one or more operating parameters of block (e.g. associated with adjusting the operation of voltage regulator: [0023]-[0024]); and provides the telemetry output (e.g. associated with providing signaling for adjusting operations of voltage regulator: [0023]-[0024]) ([0022]-[0025]; and [0046]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include MUSLEH’s interchangeable architecture, and Atsatt’s voltage regulating architecture into Zaman’s computing system for the benefit of enabling an hybrid design that can mix and match different technology (MUSLEH, [0183]), and improving power management capabilities (Atsatt, [0025]) to obtain the invention as specified in claim 25.
Claims 11, 13-14 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Zaman et al. (US Pub.: 2020/0328192) in view of MUSLEH et al. (US Pub.: 2021/0092069), and Atsatt et al. (US Pub.: 2019/0041923) as applied to claim 1 above, and further in view of Clark et al. (US Pub.: 2019/0140648).
As per claims 11, 13-14, and 22-23, Zaman, MUSLEH and Atsatt teach/suggest all the claimed features of claim 21 above, where Zaman, MUSLEH and Atsatt further teach/suggest the computing system comprising: the globals block is configured to provide a signal to at least one functional block of the plurality of functional blocks; wherein the globals block operates according; and wherein the globals block operates according (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]), but Zaman, MUSLEH and Atsatt do not teach the computing system comprising: a dynamic frequency scaling signal; comprises clock generation and distribution circuitry; comprises debug circuitry; wherein the parameter is temperature or an indication of temperature, and wherein the signal comprises a dynamic frequency scaling signal; and wherein the parameter is provided by clock generation circuitry, and wherein the signal is a clock signal.
Clark teach/suggest a system comprising: a dynamic frequency scaling signal ([0062]); comprises clock generation and distribution circuitry ([0089]-[0091]); comprises debug circuitry ([0051]; [0097]-[0098]); wherein the parameter is temperature or an indication of temperature, and wherein the signal comprises a dynamic frequency scaling signal ([0062]); and wherein the parameter is provided by clock generation circuitry, and wherein the signal is a clock signal (e.g. associated with dynamic voltage and frequency scaling scheme, wherein the desired frequency for corresponding clock signal is provided: [0062]) (Fig. 3; [0030]; [0034]-[0043]; [0051]; [0062]; [0089]-[0091]; [0097]-[0098]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Clark’s various functionality into Zaman, MUSLEH and Atsatt’s computing system method for the benefit of implementing a more robust architecture by further incorporating additional IP blocks while implementing high speed interfaces for reading or writing data (Clark, [0029]-[0030]) to obtain the invention as specified in claims 11, 13-14, and 22-23.
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zaman et al. (US Pub.: 2020/0328192) in view of MUSLEH et al. (US Pub.: 2021/0092069), and Atsatt et al. (US Pub.: 2019/0041923) as applied to claim 1 above, and further in view of Van Der Veen (US Pub.: 2003/0127607).
As per claims 12 and 19, Zaman, MUSLEH and Atsatt teach/suggest all the claimed features of claim 1 above, where Zaman, MUSLEH and Atsatt further teach/suggest the computing system comprising: wherein the globals block operate accordingly; and wherein a system includes the array (Zaman, 5-7; [0014]-[0026]; [0033]-[0038]; [0046]-[0060]; MUSLEH, [0169]-[0183]; [0286]; and Atsatt, [0022]-[0025]; [0046]), but Zaman, MUSLEH and Atsatt do not expressly teach the computing system comprising: comprises a mask alignment target; and system on a wafer.
Van Der Veen teaches/suggests a system comprising: comprises a mask alignment target; and system on a wafer ([0008]-[0009]; [0023]; and [0033]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Van Der Veen’s alignment and wafer into man, MUSLEH and Atsatt’s system for the benefit of improving delivery of correct dose at substrate level and improving uniformity when manufacturing integrated circuits (Van Der Veen, [0015]-[0017]; and [0023]) to obtain the invention as specified in claims 12 and 19.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 June 02, 2026
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