Prosecution Insights
Last updated: October 02, 2026
Application No. 18/683,889

VERTICAL CAVITY LIGHT-EMITTING ELEMENT

Non-Final OA §102§103§112
Filed
Feb 15, 2024
Priority
Aug 20, 2021 — JP 2021-135105 +1 more
Examiner
MANNO, JESSICA S
Art Unit
Tech Center
Assignee
Stanley Electric Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
146 granted / 202 resolved
+12.3% vs TC avg
Strong +27% interview lift
Without
With
+27.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
13 currently pending
Career history
221
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 202 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 5, it is not clear what is meant by the limitation “stripe core substrate” as this does not appear to be a term or art or defined by the specification. For purposes of examination, it is assumed that a substrate with sections of different shapes. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka WO 2020/184148. (For purposes of this rejection, the 371 National stage Tanaka US PGPUB 2022/0166191, herein after Tanaka ‘191, will be referred to in the rejection below.) Regarding claim 1, Tanaka ‘191 discloses a vertical cavity light-emitting element (Figure 1, [0001], [0108]) comprising: a gallium-nitride-based semiconductor substrate (11, [0118]); a first multilayer reflector (41) made of a nitride semiconductor formed on the substrate ([0103], [0124]); a semiconductor structure layer including a first semiconductor layer (21), an active layer (23), and a second semiconductor layer (22), the first semiconductor layer (21) being made of a nitride semiconductor having a first conductivity type (n-type) formed on the first multilayer reflector (Figure 1, [0119], layer 21 is over layer 41 and thus “on” the reflector 41), the active layer (23) being made of a nitride semiconductor ([0131]) formed on the first semiconductor layer (Figure 1), the second semiconductor layer (22) being formed on the active layer (23) and made of a nitride semiconductor having a second conductivity type (p-type) opposite to the first conductivity type (Figure 1, [0119], layer 22 is over active layer 23 and thus “on” the active layer); a first electrode layer (31) electrically in contact with the first semiconductor layer of the semiconductor structure layer ([0111]); a second electrode layer (32) formed on an upper surface of the semiconductor structure layer (Figure 1), the second electrode layer being electrically in contact with the second semiconductor layer ([0101], [0112], [0119]) of the semiconductor structure layer in one region of the upper surface of the semiconductor structure layer (Shown in Figure 1); and a second multilayer reflector (42) formed on the second electrode layer to cover the one region (Figure 1, [0103], [0124]), the second multilayer reflector configuring a resonator between the first multilayer reflector and the second multilayer reflector ([0105], [0119], [128]), wherein: an upper surface of the gallium-nitride-based semiconductor substrate is a surface offset from a c-plane to any one of crystal planes of an m-plane or an a-plane ([0093-0097], Table 1 and Figures 271-e), and the one region has: a shape having a longitudinal direction in an m-axis direction when the upper surface of the gallium-nitride-based semiconductor substrate is offset to the m-plane, and a shape having a longitudinal direction in an a-axis direction when the upper surface of the gallium-nitride-based semiconductor substrate is offset to the a-plane ([0093-0099], [0101] and [0105], wherein the size and shape of the current constriction region is adjusted as claimed, including an elongated/ellipse/oval shape). Regarding claim 2, Tanaka ‘191 further discloses a plurality of slit-shaped recessed portions parallel to one another are formed in a region on a lower surface of the gallium-nitride-based semiconductor substrate (protrusions formed on the bottom of substrate 11, Figure 1), the region on which the plurality of slit-shaped recessed portions are formed overlapping with the one region when viewed in a normal direction of the gallium-nitride-based semiconductor substrate (Figure 1), and each of the slit-shaped recessed portions has: a longitudinal direction in the m-axis direction when the upper surface of the gallium-nitride-based semiconductor substrate is offset to the m-plane, and a longitudinal direction in the a-axis direction when the one upper surface of the gallium-nitride-based semiconductor substrate is offset to the a-plane ([0087],[0093] and [0119]). Regarding claim 3, Tanaka ‘191 further discloses a region that is on a lower surface of the gallium-nitride-based semiconductor substrate (11) and overlaps with the one region when viewed in a normal direction of the gallium-nitride-based semiconductor substrate has a convex lens shape projecting downward (See Figure 1). Regarding claim 5, Tanaka ‘191 further discloses that the gallium-nitride-based semiconductor substrate is a stripe core substrate (As this claim is understood, substrate 11 meets this limitation), and a direction in which a core of the gallium-nitride-based semiconductor substrate extends is: a direction along the m-axis when the upper surface is offset to the m-plane, and a direction along the a-axis when the upper surface is offset to the a-plane ([0093-0097], Table 1 and Figures 271-e). Regarding claim 6, Tanaka ‘191 further discloses that the one region is in has an oval shape ([0093-0099], [0101] and [0105], wherein the size and shape of the current constriction region is adjusted as claimed, including an elongated/ellipse/oval shape). Regarding claim 7, Tanaka ‘191 further discloses that the one region is in has a rectangular shape ([0093-0099], [0101] and [0105], wherein the size and shape of the current constriction region is adjusted as claimed, including an elongated rectangular shape). Regarding claim 8, Tanaka ‘191 discloses a vertical cavity light-emitting element (Figure 1, [0001], [0108]) comprising: a gallium-nitride-based semiconductor substrate (11, [0118]); a first multilayer reflector (41) made of a nitride semiconductor formed on the substrate ([0103], [0124]); a semiconductor structure layer including a first semiconductor layer (21), an active layer (23), and a second semiconductor layer (22), the first semiconductor layer (21) being made of a nitride semiconductor having a first conductivity type (n-type) formed on the first multilayer reflector (Figure 1, [0119], layer 21 is over layer 41 and thus “on” the reflector 41), the active layer (23) being made of a nitride semiconductor ([0131]) formed on the first semiconductor layer (Figure 1), the second semiconductor layer (22) being formed on the active layer (23) and made of a nitride semiconductor having a second conductivity type (p-type) opposite to the first conductivity type (Figure 1, [0119], layer 22 is over active layer 23 and thus “on” the active layer); a first electrode layer (31) electrically in contact with the first semiconductor layer of the semiconductor structure layer ([0111]); a second electrode layer (32) formed on an upper surface of the semiconductor structure layer (Figure 1), the second electrode layer being electrically in contact with the second semiconductor layer ([0101], [0112], [0119]) of the semiconductor structure layer in one region of the upper surface of the semiconductor structure layer (Shown in Figure 1); and a second multilayer reflector (42) formed to cover the one region on the second electrode layer (Figure 1, [0103], [0124]), the second multilayer reflector configuring a resonator between the first multilayer reflector and the second multilayer reflector ([0105], [0119], [128]), wherein: an upper surface of the gallium-nitride-based semiconductor substrate is a surface offset from a c-plane to any one of crystal planes of an m-plane or an a-plane ([0093-0097], Table 1 and Figures 271-e), the one region is disposed so as to be in a shape of 2n-fold symmetry (n > 1) having a first line symmetry axis and a second line symmetry axis, and a direction of an axis having the longest length overlapping with the one region of the first line symmetry axis and the second line symmetry axis is (([0093-0099], [0101] and [0105], Figure 27a-e): an m-axis direction when the upper surface of the gallium-nitride- based semiconductor substrate is offset to the m-plane, and an a-axis direction when the upper surface of the gallium-nitride- based semiconductor substrate is offset to the a-plane ([0093-0099], [0101] and [0105], wherein the size and shape of the current constriction region is adjusted as claimed, including an elongated/ellipse/oval shape). Regarding claim 9, Tanaka ‘191 further discloses that the one region is disposed to be in a shape surrounding a region in which the second electrode layer is not in electric contact with the second semiconductor layer (Figure 1 and ([0093-0099], [0101] and [0105], wherein the current constriction region shape is adjusted as claimed). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka WO 2020/184148. (For purposes of this rejection, the 371 National stage Tanaka US PGPUB 2022/0166191, herein after Tanaka ‘191, will be referred to in the rejection below) in view of WO 2021/140871, herein after Kuramoto ‘871. Regarding claim 4, Tanaka ‘191 does not specifically disclose that upper surface of the gallium-nitride-based semiconductor substrate is: a surface offset by an angle of 0.8 degrees or less from the c-plane to the m-plane when the upper surface is offset to the m-plane, and a surface offset by an angle of 0.8 degrees or less from the c-plane to the a-plane when the upper surface is offset to the a-plane. However, in the same field of endeavor, Kuramoto ‘871 discloses that upper surface of the gallium-nitride-based semiconductor substrate (11) is: a surface offset by an angle of 0.8 degrees or less from the c-plane to the m-plane when the upper surface is offset to the m-plane, and a surface offset by an angle of 0.8 degrees or less from the c-plane to the a-plane when the upper surface is offset to the a-plane (Pages 19-20 of translation, main surface of 11 is tilted by 0.4 degrees, the angle of offset is preferably an inclination in the range of 0.1 to 0.5 degrees). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kuramoto ‘871 with that of Tanaka ‘191 for the purpose of increased gain centering on the desired direction to obtain a large amount of laser light (Pages 19-20 of translation, main surface of 11 is tilted by 0.4 degrees, the angle of offset is preferably an inclination in the range of 0.1 to 0.5 degrees). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSICA S MANNO whose telephone number is (571)272-2339. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kiesha Bryant can be reached at 571-272-3606. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSICA S MANNO/SPE, Art Unit 2898
Read full office action

Prosecution Timeline

Feb 15, 2024
Application Filed
Aug 13, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+27.3%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 202 resolved cases by this examiner. Grant probability derived from career allowance rate.

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