DETAILED ACTION
Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-7 and 14-22 are currently pending in this application. Claim 8-13 were cancelled in a preliminary amendment.
Priority
2. This application does not claim foreign priority. This application claims benefit to numerous applications with the oldest one being provisional application 62/614,706 filed 01/08/2018. The entire family can be seen in applicant’s specification.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 2/22/2024, 04/24/2024 and 9/12/2024 have been received. The submission is in compliance with the provisions of 37 CFR 1.97 and 37 CFR 1.98. Accordingly, the information disclosure statement has being considered by the examiner.
Drawings
4. The drawings submitted on 2/20/2024 are in compliance with 37 CFR § 1.81 and 37 CFR § 1.83 and have been accepted by the examiner.
Claim Rejections - 35 USC § 101 Non-Statutory
5. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
6. Claims 1-7 and 14-22 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Specifically, representative Claim 1 recites:
An integrated circuit (IC) comprising:
a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different values of remaining margins of the multiple data paths or different ranges of remaining margins of the multiple data paths; and
a system configured to adjust a clock frequency of the IC and/or a voltage of the IC based at least on the output of said margin measurement circuit.
The claim limitations in the abstract idea have been highlighted in bold above; the remaining limitations are “additional elements.”
Similar limitations comprise the abstract ideas of Claim 15.
Under Step 1 of the analysis, claim 1 does belong to a statutory category, namely it is a process claim. Likewise, claim 8 is a system claim and claim 15 a non-transitory computer readable medium claim.
Under Step 2A, prong 1, claim 1 is found to include at least one judicial exception, that being a mathematical concept and/or mental process. This can be seen in the claim limitation of “a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different values of remaining margins of the multiple data paths or different ranges of remaining margins of the multiple data paths; and a system configured to adjust a clock frequency of the IC and/or a voltage of the IC based at least on the output of said margin measurement circuit”, which is the judicial exception of a mental process and/or a mathematical concept because it is merely a data evaluation including calculations, and/or judgements capable of being performed mentally.
Similar limitations comprise the abstract ideas of Claim 15.
Step 2A, prong 2 of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception(s) into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application.
In addition to the abstract ideas recited in claim 1, the claimed method recites additional elements including “a margin measurement circuit” (claims 1 & 15) which are merely data gathering steps recited at a high level of generality and therefore merely amount to “insignificant extra-solution” activity(ies). See MPEP 2106.05(g) “Insignificant Extra-Solution Activity,”. The claim also recites “,a system and a computer” (claims 1 and/or 15) however the “system and computer” are recited at a high level of generality, and merely amounts to the use of computer technology as a tool to apply the abstract idea (see MPEP 2106.05(f)) and/or the use of “a system” or a “computer” to perform the predictions, that are otherwise abstract, is merely an attempt at limiting the abstract to a particular field of use (See MPEP 2106.05(h)).
The generic data gathering, processing, and output steps, and other elements, are recited so generically (no details whatsoever are provided) that it represents no more than mere instructions to apply the judicial exceptions on a computer. It can also be viewed as nothing more than an attempt to generally link the use of the judicial exceptions to the technological environment of a computer. Noting MPEP 2106.04(d)(I): “It is notable that mere physicality or tangibility of an additional element or elements is not a relevant consideration in Step 2A Prong Two. As the Supreme Court explained in Alice Corp., mere physical or tangible implementation of an exception does not guarantee eligibility. Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S. 208, 224, 110 USPQ2d 1976, 1983-84 (2014) ("The fact that a computer ‘necessarily exist[s] in the physical, rather than purely conceptual, realm,’ is beside the point")”.
Thus, under Step 2A, prong 2 of the analysis, even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception. No specific practical application is associated with the claimed system. For instance, it is unclear what adjusting the clock frequency accomplishes.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, as described above with respect to Step 2A Prong 2, merely amount to a general purpose computer system that attempts to apply the abstract idea in a technological environment, limiting the abstract idea to a particular field of use, and/or merely insignificant extra-solution activity (claims 1, 8, and 15). Such insignificant extra-solution activity, e.g. data gathering and output, when re-evaluated under Step 2B is further found to be well-understood, routine, and conventional as evidenced by MPEP 2106.05(d)(II) (describing conventional activities that include transmitting and receiving data over a network, electronic recordkeeping, storing and retrieving information from memory, and electronically scanning or extracting data from a physical document).
Therefore, similarly the combination and arrangement of the above identified additional elements when analyzed under Step 2B also fails to necessitate a conclusion that claim 1, as well as claim 15, amount to significantly more than the abstract idea.
With regards to the dependent claims, claims 2-7,14, and 16-22, merely further expand upon the algorithm/abstract idea and do not set forth further additional elements therefore these claims are found ineligible for the reasons described for independent claims 1, 8, and 15.
See Supreme court decision in Alice Corporation Pty. Ltd. V. CLS Bank International, et al.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-2 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sippel US Pat # 2013/0043916.
With regards to claim 1, Sippel US Pat # 2013/0043916 teaches an integrated circuit (IC) comprising:
a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different values of remaining margins of the multiple data paths or different ranges of remaining margins of the multiple data paths; (paragraph 0043-0044) and
a system configured to adjust a clock frequency of the IC and/or a voltage of the IC based at least on the output of said margin measurement circuit. (paragraph 0043)
With regards to claim 2, Sippel US Pat # 2013/0043916 teaches the processor is further configured, based on the computed upper and lower bounds of the current remaining margin, to estimate at least one of: degradation the multiple data paths, or a predicted time of failure of the IC due to a timing violation by a worst-performing data path of the multiple data paths.(timing failures; Paragraph 0062)
With regards to claim 15, (USPN) teaches a non-transient computer-readable medium having stored thereon a computer- readable encoding of an integrated circuit (IC), the computer-readable encoding of the IC comprising:
a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different values of remaining margins of the multiple data paths or different ranges of remaining margins of the multiple data paths;(paragraph 0043-0044) and
a system configured to adjust a clock frequency of the IC and/or a frequency of the IC based at least on the output of said margin measurement circuit. (paragraph 0043)
10. Claims 1-2 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sewall US Pat # 2010/0153896.
With regards to claim 1, Sewall US Pat # 2010/0153896 teaches an integrated circuit (IC) comprising:
a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different values of remaining margins of the multiple data paths or different ranges of remaining margins of the multiple data paths; (paragraph 0019) and
a system configured to adjust a clock frequency of the IC and/or a voltage of the IC based at least on the output of said margin measurement circuit. (paragraph 0021)
With regards to claim 2, Sewall US Pat # 2010/0153896 teaches the processor is further configured, based on the computed upper and lower bounds of the current remaining margin, to estimate at least one of:
degradation the multiple data paths, or a predicted time of failure of the IC due to a timing violation by a worst-performing data path of the multiple data paths.(timing margin violated; Paragraph 0031)
With regards to claim 15, Sewall US Pat # 2010/0153896 teaches an non-transient computer-readable medium having stored thereon a computer- readable encoding of an integrated circuit (IC), the computer-readable encoding of the IC comprising:
a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different values of remaining margins of the multiple data paths or different ranges of remaining margins of the multiple data paths;(paragraph 0019) and
a system configured to adjust a clock frequency of the IC and/or a frequency of the IC based at least on the output of said margin measurement circuit. (paragraph 0021)
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Guo et al. US 2022/0092245 teaches endpoint pat margin based integrated circuit design using subcritical timing paths.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA S BHAT whose telephone number is (571)272-2270. The examiner can normally be reached on Monday-Friday 8 am-6pm.
13. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
14. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby Turner can be reached on 571-272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
15. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADITYA S BHAT/Primary Examiner, Art Unit 2857 July 24, 2026
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