DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/26/2024, 10/31/2025, and 08/06/2026 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 and claim 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "an intermediate layer" in line 4. There is already a prior recitation of “an intermediate layer” in claim 1 on which claim 13 depends, rendering it unclear whether “an intermediate layer” of claim 13 refers to the same or a different “intermediate layer”. Therefore, for the purposes of Examination, Examiner has interpreted “an intermediate layer” in claim 13 as --- the intermediate layer ---
Claim 13 recites the limitation "a reflective electrode layer" in line 4. There is already a prior recitation of “a reflective electrode layer” in claim 1 on which claim 13 depends, rendering it unclear whether “a reflective electrode layer” of claim 13 refers to the same or a different “reflective electrode layer”. Therefore, for the purposes of Examination, Examiner has interpreted “a reflective electrode layer” in claim 13 as --- the reflective electrode layer ---
Claim 14 recites the limitation "an intermediate layer" in line 4. There is already a prior recitation of “an intermediate layer” in claim 1 on which claim 14 depends, rendering it unclear whether “an intermediate layer” of claim 14 refers to the same or a different “intermediate layer”. Therefore, for the purposes of Examination, Examiner has interpreted “an intermediate layer” in claim 14 as --- the intermediate layer ---
Claim 14 recites the limitation "a reflective electrode layer" in line 4. There is already a prior recitation of “a reflective electrode layer” in claim 1 on which claim 14 depends, rendering it unclear whether “a reflective electrode layer” of claim 14 refers to the same or a different “reflective electrode layer”. Therefore, for the purposes of Examination, Examiner has interpreted “a reflective electrode layer” in claim 14 as --- the reflective electrode layer ---
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, and 6-15 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seong (U.S. PG Pub No US2008/0303055A1).
Regarding claim 1, Seong teaches a stacked body (comprising 100, 70, 80) fig. 5 [0077-0078], comprising;
a reflective electrode layer (80) fig. 5 [0074] (may be formed of reflective metal [0026] such as gold [0074, 0026]), an intermediate layer (TCO layer of 70 multilayer) fig. 5 [0064, 0067] (intermediate between 80 and 100) having a MgZnO composition [0067], and a semiconductor layer (100) fig. 5 [0081] having an AlGaN (when c, x, y, z = 0 ) [0081] composition in this order (from top to bottom),
wherein a thickness of the intermediate layer (TCO layer of 70) is 1-80 nm (1-1000 nm [0071], which encompasses the claimed range).
With respect to whether Seong teaches “a thickness of the intermediate layer is 1-80 nm”, Seong does not specifically disclose recited range of 1-80 nm for the thickness of the intermediate layer. However, Seong discloses that a thickness of the intermediate layer 70 may be 1-1000nm [0072], which encompasses the claimed range of 1-80nm. Therefore, in the absence of evidence of criticality for the narrower range recited in the claims, one of ordinary skill in the art would consider the recited range sufficiently within the scope of the teachings of Seong. (See MPEP 2144.05, I).
Regarding claim 3, Seong teaches the stacked body [see fig. 5, 0077-0078] of claim 1. Seong also teaches wherein the intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] comprises an oxide of magnesium and an oxide of zinc (could comprise combination of MgO and ZnO oxide [0067]).
Regarding claim 4, Seong teaches the stacked body [see fig. 5, 0077-0078] of claim 1. Seong also teaches wherein the intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] has a MgZnO composition of MgXZnyO (x is 0.2 to 0.8, y is 0.8 to 0.2) (could comprise ‘combination’ of MgO and ZnO oxide and/or MgZnO [0067], i.e, could be Mg0.5Zn0.5O).
Regarding claim 6, Seong teaches a method [0075] of producing the stacked body (comprising 100, 70, 80) fig. 5 [0077-0078] of claim 1, comprising depositing [0072-0075], the intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] on (supported by) the semiconductor layer (100) fig. 5 [0081].
Regarding claim 7, Seong teaches the method [0075] of producing of claim 6. Seong also teaches wherein the intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] is formed by sputtering [0075].
Regarding claim 8, Seong teaches the method [0075] of producing of claim 6. Seong also teaches
wherein a surface temperature [0072-0073] of the semiconductor layer (100) fig. 5 [0081] (at equilibrium with deposition conditions [0072]) at a time of forming the intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] is 20*C or higher (20-1500C) [0073].
For the purposes of Examination, it is assumed that the “?” mark character employed in [0072-0073] of Seong corresponds to a “Celsius” temperature C). As evidence that this is a reasonable assumption, see [0005, 0032, 0043] of Robin (U.S. PG Pub No US2018/0301479A1), which discusses typical temperature treatment ranges for deposition and annealing in LED package on the order of a few hundred to ~ 1000 degrees Celsius.
Regarding claim 9, Seong teaches the method [0075] of producing of claim 6. Seong also teaches
wherein a surface temperature [0072-0073] of the semiconductor layer (100) fig. 5 [0081] at a time of forming the intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] is 180*C or higher (20-1500C, overlaps the claimed range) [0073].
With respect to whether Seong teaches “a surface temperature of the semiconductor layer at a time of forming the intermediate layer is 180*C or higher”, Seong does not specifically disclose recited range of 180*C or more for the temperature. However, Seong discloses that the temperature of the reactor may be 20-1500C [0073], which overlaps with the claimed range of >180*C [0073]. Therefore, in the absence of evidence of criticality for the specific temperature range recited in the claims, one of ordinary skill in the art would consider the recited range sufficiently within the scope of the teachings of Seong. (See MPEP 2144.05, I).
Regarding claim 10, Seong teaches the method [0075] of producing of claim 6. Seong also teaches comprising heat-treating the formed intermediate layer (TCO layer of 70) fig. 5 [0064, 0067] at a temperature of 600*C or higher (100-800C, which overlaps with the >600C).
With respect to whether Seong teaches “heat-treating the formed intermediate layer at a temperature of 600*C or higher”, Seong does not specifically disclose recited range of 600*C or more for the temperature. However, Seong discloses that the temperature of the reactor may be 100-800*C [0072-0073], which overlaps with the claimed range of >600*C [0073]. Therefore, in the absence of evidence of criticality for the specific temperature range recited in the claims, one of ordinary skill in the art would consider the recited range sufficiently within the scope of the teachings of Seong. (See MPEP 2144.05, I).
Regarding claim 11, Seong teaches an emitting (light-emitting) device [see fig. 5, 0077] comprising the stacked body (comprising 100, 70, 80) fig. 5 [0077-0078] according to claim 1.
Regarding claim 12, Seong teaches the emitting device [see fig. 5, 0077] of claim 11. Seong also teaches comprising a stacked structure [see fig. 5, 0077] having a substrate (10) fig. 5 [0076], an n-type contact layer (contact layer provided between 40 and 90) fig. 5 [0061, 0076] (not explicitly shown), an emitting layer (50) fig. 5 [0059-0060] (active layer form light emission [0059, 0075-0076]), and the stacked body (comprising 100, 70, 80) fig. 5 [0077-0078] in this order, and an electrode layer (90) fig. 5 [0061, 0076] formed on (so as to overlap) a part of the n-type contact layer (90) on which the emitting layer (50) is not formed (50 not formed on/ to overlap 90).
Regarding claim 13, Seong teaches the emitting device [see fig. 5, 0077] of claim 11. Seong also teaches comprising a stacked structure [see fig. 5, 0077] having a substrate (10) fig. 5 [0076], an n-type contact layer (contact layer provided between 40 and 90) fig. 5 [0061, 0076] (not explicitly shown), an emitting layer (50) fig. 5 [0059-0060] (active layer for light emission [0059, 0075-0076]), a p- type semiconductor layer (60) fig. 5 [0055, 0060] (p-type GaN [0060]), and
an electrode layer (lower, metal-comprising contact layer 70) fig. 5 [0062, 0064, 0067] in this order (from bottom to top), and the intermediate layer (TCO layer of 70 multilayer) fig. 5 [0064, 0067] having a MgZnO composition [0067], and the reflective electrode layer (80) fig. 5 [0074] on a part of the n-type contact layer (90) on which the emitting layer (50) is not formed (50 not formed on/ to overlap 90) in this order,
wherein the part of the n-type contact layer (contact layer provided between 40 and 90), the intermediate layer (TCO layer of 70 multilayer) having a MgZnO composition [0067] (TCO layer of 70 multilayer), and the reflective electrode layer (80) fig. 5 [0074] form (compose portions of) the stacked body (comprising contact layer between 40 and 90, 100, 70, 80) fig. 5 [0077-0078].
Regarding claim 14, Seong teaches an (light) emitting device [see fig. 5, 0077] of claim 11. Seong also teaches comprising a stacked structure [see fig. 5, 0077] having a substrate (10) fig. 5 [0076], an n-type contact layer (contact layer provided between 40 and 90) fig. 5 [0061, 0076] (not explicitly shown), an emitting layer (50) fig. 5 [0059-0060] (active layer for light emission [0059, 0075-0076]), and the stacked body (comprising 100, 70, 80) fig. 5 [0077-0078] in this order (from bottom to top), and
the intermediate layer (TCO layer of 70 multilayer) fig. 5 [0064, 0067] having a MgZnO composition [0067] and the reflective electrode layer (80) on a part of the n-type contact layer (contact layer provided between 40 and 90) on which the emitting layer (50) is not formed in this order,
wherein the part of the n-type contact layer (contact layer provided between 40 and 90), the intermediate layer (TCO layer of 70 multilayer) having a MgZnO composition [0067], and the reflective electrode layer (80) form (compose portions of) the stacked body (comprising contact layer between 40 and 90, 100, 70, 80) fig. 5 [0077-0078].
Regarding claim 15, Seong teaches the (light) emitting device [see fig. 5, 0077] of claim 12. Seong also teaches comprising a p-type semiconductor layer (60) fig. 5 [0055, 0060] (p-type GaN [0060]) between the emitting layer (50) fig. 5 [0059-0060] and the stacked body (comprising 90, 100, 70, 80) fig. 5 [0077-0078].,
wherein the p-type semiconductor layer (60) and the semiconductor layer (100) fig. 5 [0082-0083] of the stacked body form a tunnel junction structure [0080-0081].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Seong (U.S. PG Pub No US2008/0303055A1), as applied in claim 1 above, in view of Chu (U.S. PG Pub No US2013/0292718A1).
Regarding claim 2, Seong teaches the (light) emitting device [see fig. 5, 0077] of claim 1. However, Seong does not explicitly disclose wherein the reflective electrode layer (80) fig. 5 [0074] (may be formed of reflective metal [0026] like gold [0074, 0026]) comprises at least one metal selected from the group consisting of Al, Rh, Mo, W, and Cr (other choices mentioned [0026]).
Chu teaches an emitting device [see fig. 2, 0074] wherein the reflective electrode layer (236) fig. 2 [0075] (formed of reflective metal) comprises at least one metal selected from the group consisting of Al, Rh, Mo, W, and Cr (comprises a sublayer composed only of Cr [0074] in addition to a sublayer of pure Au).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Seong such that the gold reflective electrode layer is modified to have an additional sublayer composed only of chromium [0074] in order to selectively enhance the conductivity properties of the electrode [0074] by varying material composition of stack [0074], as taught by Chu.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure they all feature LED structures with mesas and reflective electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/30/2026
Prosecution Insights