CTNF 18/685,521 CTNF 80387 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 22, 2024 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The examiner notes that the applicant has submitted both JPS62-196823A and JPS62-196823U while only listing JPS62-196823A on the IDS. The examiner further notes the JPS62-196823U has not been considered by the examiner. Drawings 06-22-06 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: reference number 2 for a first surface electrode mentioned in paragraphs 15 and 71, reference number 3 for a second surface electrode mentioned in paragraphs 15 and 71, reference number 5 for an electroconductive layer mentioned in paragraphs 17 and 71, and reference number 9 for a reverse-surface electrode mentioned in paragraphs 24 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 4 and 12-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites the Markush Group “made of polyimide or polybenzoxazole,” on page 5 lines 4-5. The Markush Group renders the claim indefinite because it is unclear what elements are included in the Markush Group. The examiner first notes that, “Although the term "Markush claim" is used throughout the MPEP, any claim that recites alternatively usable members, regardless of format, should be treated as a Markush claim.” See MPEP § 2117 I. The examiner next notes that the Markush Group is presumptively open-ended because of the use of the transitional phrase, “comprising,” in independent claim 1, thus, the Markush Group includes additional unrecited elements. The examiner now notes that “If a Markush grouping requires a material selected from an open list of alternatives (e.g., selected from the group ‘comprising’ or ‘consisting essentially of’ the recited alternatives), the claim should generally be rejected under 35 U.S.C. 112(b) as indefinite because it is unclear what other alternatives are intended to be encompassed by the claim.” See MPEP § 2173.05(h) I. Claim 12 recites the Markush Group “made of silicon, silicon carbide, gallium arsenide, gallium nitride, or gallium oxide,” on page 6 lines 9-10. The Markush Group renders the claim indefinite because it is unclear what elements are included in the Markush Group. The examiner first notes that, “Although the term "Markush claim" is used throughout the MPEP, any claim that recites alternatively usable members, regardless of format, should be treated as a Markush claim.” See MPEP § 2117 I. The examiner next notes that the Markush Group is presumptively open-ended because of the use of the transitional phrase, “comprising,” in independent claim 1, thus, the Markush Group includes additional unrecited elements. The examiner now notes that “If a Markush grouping requires a material selected from an open list of alternatives (e.g., selected from the group ‘comprising’ or ‘consisting essentially of’ the recited alternatives), the claim should generally be rejected under 35 U.S.C. 112(b) as indefinite because it is unclear what other alternatives are intended to be encompassed by the claim.” See MPEP § 2173.05(h) I. Claim 13 recites the limitations “converts an input power and outputs the same,” on page 6 line 15, “a drive circuit that outputs a drive signal for driving the semiconductor apparatus to the semiconductor apparatus,” on page 6 lines 16-17, and “a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit,” on page 6 line 18. These limitations render the claim indefinite because the limitations, respectively, recite the acts of converting and outputting power, outputting a drive signal, and outputting a control signal in an apparatus claim. When both an apparatus and a method are claimed in the same claim it is unclear whether infringement occurs when the apparatus is constructed or when the apparatus is used. Therefore, the scope of the claim is indefinite. See MPEP 2173.05(p). The examiner also notes that it would be unclear how a conversion circuit would output the same amount of power that is input to the conversion circuit because the amount of power output by a conversion circuit is reduced by losses in the conversion circuit. Claim 14 recites the limitations “the electroconductive layer,” on page 6 line 24 and “the insulating layer,” on page 6 lines 28-29. There is insufficient antecedent basis for these limitations in the claim. Claim 14 recites the limitation “forming the electroconductive layer, the first main surface between the first surface electrode and the second surface electrode, and the insulating layer covering an end portion of each of the first surface electrode and the second surface electrode on a side close to the electroconductive layer using a PVD or CVD method,” on page 6 lines 27-30. This limitation renders the claim indefinite because it is unclear if the electroconductive layer and the first main surface of the semiconductor substate are being formed by this step. The examiner notes that the electroconductive layer seems to be formed in a previously recited step in claim 14 and that a first main surface of a semiconductor substrate also seems to be previously formed because the semiconductor substrate was recited as having a first main surface in a previously recited step in claim 14. For examination purposes, this limitation will be treated as reciting forming an insulating layer covering the electroconductive layer, the first main surface between the first surface electrode and the electroconductive layer, the first main surface between the second surface electrode and the electroconductive layer, and an end portion of each of the first surface electrode and the second surface electrode on a side close to the electroconductive layer using a physical vapor deposition or a chemical vapor deposition method. Claim 16 recites the limitation “wherein, in the forming of the short-circuit prevention layer, the insulating layer covering the end portions of the first surface electrode and the second surface electrode is further covered by the short-circuit prevention layer to cause the short-circuit prevention layer to be in contact with the first surface electrode and the second surface electrode.” The examiner notes that this limitation only requires a possibility that the short-circuit prevention layer is in contact with the first surface electrode and the second surface electrode. Thus, this limitation renders the claim indefinite because it is unclear whether the short-circuit prevention layer is in contact with the first surface electrode and the second surface electrode. For examination purposes, this limitation will be interpreted as wherein, in the forming of the short-circuit prevention layer, the insulating layer covering the end portions of the first surface electrode and the second surface electrode is further covered by the short-circuit prevention layer such that the short-circuit prevention layer is in contact with the first surface electrode and the second surface electrode. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 6, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2007/0114577) in view of Nakata et al. (US 2017/0076948) . Regarding Claim 1: Narazaki discloses a semiconductor apparatus comprising: a semiconductor substrate (semiconductor chip having an n-type epitaxial layer and a p-type well region, See figs. 1-2, ref. no. 1, fig. 5, ref. nos. 1, 31-32, paragraphs 41 and 47) having a first main surface (top surface of the semiconductor chip, See figs. 2, 5, ref. no. 1) and a second main surface (bottom surface of the semiconductor chip, See figs. 2, 5, ref. no. 1) which is an opposite surface to the first main surface; a first surface electrode (left emitter electrode, See fig. 5, ref. no. 2 and paragraph 41) formed on the first main surface; a second surface electrode (right emitter electrode, See fig. 5, ref. no. 2 and paragraph 41) formed separately from the first surface electrode in a planar view and electrically insulated from the first surface electrode (the right emitter electrode is electrically insulated from the left emitter electrode by an inter-layer insulating layer, an overcoat layer, and a polyimide layer, See fig. 5, ref. nos. 2, 4, 5, 13, 22, paragraphs 42 and 47-48); an electroconductive layer (gate wiring layer, See figs. 1, 5, ref. no. 4 and paragraph 41) having an electroconductive property (the gate wiring layer is made of a conductive metal such as aluminum, thus, the gate wiring layer has an electroconductive property, See paragraph 41) formed on the first main surface between the first surface electrode and the second surface electrode with a space from the first surface electrode and the second surface electrode in a planar view (the gate wiring layer is formed on the top surface of the semiconductor chip between the left emitter electrode and the right emitter electrode with a space between the gate wiring layer and the left emitter electrode and the gate wiring layer and the right emitter electrode, See fig. 5, ref. nos. 2 and 4); an insulating layer (overcoat layer, See fig. 5, ref. no. 5 and paragraph 42) having an insulating property (the overcoat layer is made of insulting material such as silicon dioxide and silicon nitride, thus, the overcoat layer has an insulating property, See paragraph 42) formed to cover the electroconductive layer, the first main surface between the first surface electrode and the second surface electrode, and an end portion of each of the first surface electrode and the second surface electrode on a side close to the electroconductive layer (the overcoat layer covers the gate wiring layer, the top surface of the semiconductor chip between the left emitter electrode and the right emitter electrode, and an end portion of each of the left emitter electrode and the right emitter electrode close the gate wiring layer, See fig. 5, ref. nos. 1, 2, 4, and 5); a short-circuit prevention layer (polyimide layer, See fig. 5, ref. no. 13 and paragraph 48) having an insulating property (the polyimide layer is an insulating material, thus, the polyimide layer has an insulating property, See paragraph 48) formed to cover the insulating layer between the first surface electrode and the electroconductive layer and the insulating layer between the second surface electrode and the electroconductive layer (the polyimide layer covers the overcoat layer between the left emitter electrode and the gate wiring layer and the overcoat layer between the right emitter electrode and the gate wiring layer, See fig. 5, ref. nos. 2, 4 5, and 13), the short-circuit prevention layer having a thickness equal to or larger than a height from a lower end to an upper end of the electroconductive layer (the polyimide layer has a thickness greater than a thickness of the gate wiring layer, See fig. 5, ref. nos. 4, 13, and paragraph 48) and being made of a material different from that of the insulating layer (the polyimide layer is made of polyimide and the overcoat layer is made of insulting material such as silicon dioxide and silicon nitride, See paragraphs 42 and 48); a metal layer (metal layer, See fig. 5, ref. no. 6 and 43) formed on each of the first surface electrode and the second surface electrode; and a reverse-surface electrode (collector electrode, See fig. 2, ref. no. 7 and paragraph 45) formed on the second main surface. Narazaki does not disclose a metal plating layer formed on each of the first surface electrode and the second surface electrode (The examiner notes that this claim limitation is being interpretated as a product by process limitation with the final product being a metal layer.) Nakata discloses a nickel plating film formed on an emitter electrode by electroless nickel plating (See fig. 6, ref. no. 14 and paragraph 41). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor apparatus of Narazaki to include electroless plating of the metal layers on the left emitter electrode and the right emitter electrode as taught by Nakata in order to increase uniformity of the metal layers. Regarding Claim 2: Narazaki discloses wherein the short-circuit prevention layer (the polyimide layer covers the overcoat layer coving the gate wiring layer, See fig. 5, ref. nos. 4, 5, and 13) is formed to further cover the insulating layer covering the electroconductive layer. Regarding Claim 3: Narazaki discloses wherein the short-circuit prevention layer (the polyimide layer covers the overcoat layer covering the end portions of the left emitter electrode and the right emitter electrode and the polyimide layer has regions in contact with the left emitter electrode and the right emitter electrode, See fig. 5, ref. nos. 2, 5, and 13) is formed to further cover the insulating layer covering the end portions of the first surface electrode and the second surface electrode, and has regions in contact with the first surface electrode and the second surface electrode. Regarding Claim 4: Narazaki discloses wherein the short-circuit prevention layer is made of polyimide (the polyimide layer is made of polyimide, See paragraph 48) or polybenzoxazole. Regarding Claim 6: Narazaki discloses the gate wiring layer has a thickness, the left emitter electrode has a thickness, and the right emitter electrode has a thickness. (See fig. 5, ref. nos. 2 and 4.) Narazaki does not disclose the gate wiring layer has a thickness the same as thicknesses of the left emitter electrode and the right emitter electrode. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have gate wiring layer having a thickness the same as thicknesses of the left emitter electrode and the right emitter electrode in order to simplify the design of the semiconductor apparatus without changing how the semiconductor apparatus operates, since it has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Regarding Claim 9: Narazaki discloses a horizontal distance between the overcoat layer covering the left emitter electrode and the overcoat layer covering the gate wiring layer and a horizontal distance between the overcoat layer covering right emitter electrode and the overcoat layer covering the gate wiring layer. (See fig. 5, ref. nos. 2, 4, and 5.) Narazaki does not disclose at least one of a horizontal distance between the overcoat layer covering the left emitter electrode and the overcoat layer covering the gate wiring layer and a horizontal distance between the overcoat layer covering right emitter electrode and the overcoat layer covering the gate wiring layer is from 1 µm to 30 µm. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of a horizontal distance between the overcoat layer covering the left emitter electrode and the overcoat layer covering the gate wiring layer and a horizontal distance between the overcoat layer covering right emitter electrode and the overcoat layer covering the gate wiring layer is from 1 µm to 30 µm in order to further electrically isolate the gate wiring layer from the left emitter electrode or right emitter electrode with changing how the semiconductor apparatus operates since it has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Regarding Claim 10: Narazaki discloses a height from a lower end of the gate wiring layer to an upper end of the overcoat layer covering the gate wiring layer. (See fig. 5, ref. nos. 4 and 5). Narazaki does not disclose a height from a lower end of the gate wiring layer to an upper end of the overcoat layer covering the gate wiring layer is from 0.5 µm to 10 µm inclusive. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a height from a lower end of the gate wiring layer to an upper end of the overcoat layer covering the gate wiring layer of 0.5 µm to 10 µm inclusive in order to increase the current carrying capacity of the gate wiring layer by increasing the cross sectional area of the gate wiring layer since it has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Regarding Claim 11: Narazaki discloses the left emitter electrode and the right emitter electrode have a thickness and the gate wiring layer has a thickness. Narazaki does not disclose the left emitter electrode and the right emitter electrode each have a thickness of 1 µm to 10 µm inclusive and the gate wiring layer has a thickness of 5 µm inclusive to 40 µm inclusive. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the left emitter electrode and the right emitter electrode each have a thickness of 1 µm to 10 µm inclusive and the gate wiring layer has a thickness of 5 µm inclusive to 40 µm inclusive in order to increase the current carrying capacity of the left emitter electrode, the right emitter electrode, and the gate wiring layer by increasing the cross sectional area of the left emitter electrode, the right emitter electrode, and the gate wiring layer since it has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984) . 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2007/0114577) in view of Nakata et al. (US 2017/0076948) further in view of Gao et al. (US 2015/0091061) . Regarding Claim 5: The above stated combination of Narazaki and Nakata discloses the above stated semiconductor apparatus. The above stated combination of Narazaki and Nakata does not disclose wherein a surface of the short-circuit prevention layer is hydrophobic. Gao discloses forming a layer of hydrophobic material over a dielectric layer formed over a semiconductor structure (See fig. 3A, ref. nos. 2, 5, 6, paragraphs 30 and 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor apparatus of Narazaki and Nakata to include a layer of hydrophobic material in place of the polyimide layer as taught by Gao in order to protect the semiconductor apparatus from water. (See Gao abstract.) 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2007/0114577) in view of Nakata et al. (US 2017/0076948) further in view of Ryu et al. (US 2018/0204945) . Regarding Claim 12: The above stated combination of Narazaki and Nakata discloses the above stated semiconductor apparatus. The above stated combination of Narazaki and Nakata does not disclose wherein the semiconductor substrate is made of silicon, silicon carbide, gallium arsenide, gallium nitride, or gallium oxide and has a thickness of 50 µm inclusive to 100 µm inclusive. Ryu discloses a semiconductor substrate is made of silicon (SiC, See fig. 7, ref. no. 36, paragraphs 41 and 43), silicon carbide silicon (SiC, See fig. 7, ref. no. 36, paragraphs 41 and 43), gallium arsenide, gallium nitride, or gallium oxide and has a thickness of 50 µm inclusive to 100 µm inclusive (the substrate may range in thickness from 1µm to 400 µm, See paragraph 43). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor apparatus of Narazaki and Nakata to include the semiconductor substrate is made of silicon, silicon carbide, gallium arsenide, gallium nitride, or gallium oxide and has a thickness of 50 µm inclusive to 100 µm inclusive as taught by Ryu for ease of manufacturing of the semiconductor apparatus by using an existing semiconductor substrate . 07-21-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nagahisa (US 2020/0312995) in view of Narazaki (US 2007/0114577) and Nakata et al. (US 2017/0076948) . Regarding Claim 13: Nagahisa discloses a main conversion circuit (main conversion circuit, See fig. 26, ref. no. 201 and paragraph 66) that and converts an input power and outputs the same (the main conversion circuit converts DC power into AC power, See paragraph 166); a drive circuit (drive circuit which outputs a drive signal for driving each switching element in the main conversion circuit, See fig. 26, ref. no. 202) that outputs a drive signal for driving the semiconductor apparatus to the semiconductor apparatus; and a control circuit (control circuit which outputs to the drive circuit a control signal for controlling the drive circuit, See fig. 26, ref. no. 203) that outputs a control signal for controlling the drive circuit to the drive circuit. Nagahisa does not disclose the main conversion circuit include a semiconductor apparatus according to claim 1. Narazaki discloses a semiconductor apparatus comprising: a semiconductor substrate (semiconductor chip having an n-type epitaxial layer and a p-type well region, See figs. 1-2, ref. no. 1, fig. 5, ref. nos. 1, 31-32, paragraphs 41 and 47) having a first main surface (top surface of the semiconductor chip, See figs. 2, 5, ref. no. 1) and a second main surface (bottom surface of the semiconductor chip, See figs. 2, 5, ref. no. 1) which is an opposite surface to the first main surface; a first surface electrode (left emitter electrode, See fig. 5, ref. no. 2 and paragraph 41) formed on the first main surface; a second surface electrode (right emitter electrode, See fig. 5, ref. no. 2 and paragraph 41) formed separately from the first surface electrode in a planar view and electrically insulated from the first surface electrode (the right emitter electrode is electrically insulated from the left emitter electrode by an inter-layer insulating layer, an overcoat layer, and a polyimide layer, See fig. 5, ref. nos. 2, 4, 5, 13, 22, paragraphs 42 and 47-48); an electroconductive layer (gate wiring layer, See figs. 1, 5, ref. no. 4 and paragraph 41) having an electroconductive property (the gate wiring layer is made of a conductive metal such as aluminum, thus, the gate wiring layer has an electroconductive property, See paragraph 41) formed on the first main surface between the first surface electrode and the second surface electrode with a space from the first surface electrode and the second surface electrode in a planar view (the gate wiring layer is formed on the top surface of the semiconductor chip between the left emitter electrode and the right emitter electrode with a space between the gate wiring layer and the left emitter electrode and the gate wiring layer and the right emitter electrode, See fig. 5, ref. nos. 2 and 4); an insulating layer (overcoat layer, See fig. 5, ref. no. 5 and paragraph 42) having an insulating property (the overcoat layer is made of insulting material such as silicon dioxide and silicon nitride, thus, the overcoat layer has an insulating property, See paragraph 42) formed to cover the electroconductive layer, the first main surface between the first surface electrode and the second surface electrode, and an end portion of each of the first surface electrode and the second surface electrode on a side close to the electroconductive layer (the overcoat layer covers the gate wiring layer, the top surface of the semiconductor chip between the left emitter electrode and the right emitter electrode, and an end portion of each of the left emitter electrode and the right emitter electrode close the gate wiring layer, See fig. 5, ref. nos. 1, 2, 4, and 5); a short-circuit prevention layer (polyimide layer, See fig. 5, ref. no. 13 and paragraph 48) having an insulating property (the polyimide layer is an insulating material, thus, the polyimide layer has an insulating property, See paragraph 48) formed to cover the insulating layer between the first surface electrode and the electroconductive layer and the insulating layer between the second surface electrode and the electroconductive layer (the polyimide layer covers the overcoat layer between the left emitter electrode and the gate wiring layer and the overcoat layer between the right emitter electrode and the gate wiring layer, See fig. 5, ref. nos. 2, 4 5, and 13), the short-circuit prevention layer having a thickness equal to or larger than a height from a lower end to an upper end of the electroconductive layer (the polyimide layer has a thickness greater than a thickness of the gate wiring layer, See fig. 5, ref. nos. 4, 13, and paragraph 48) and being made of a material different from that of the insulating layer (the polyimide layer is made of polyimide and the overcoat layer is made of insulting material such as silicon dioxide and silicon nitride, See paragraphs 42 and 48); a metal layer (metal layer, See fig. 5, ref. no. 6 and 43) formed on each of the first surface electrode and the second surface electrode; and a reverse-surface electrode (collector electrode, See fig. 2, ref. no. 7 and paragraph 45) formed on the second main surface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the power converter of Nagahisa to include the semiconductor apparatus of as taught by Narazaki in order to increase reliability of the main circuit by using more reliable switching elements. (See Narazaki paragraphs 11-12.) The above stated combination of Nagahisa and Narazaki does not disclose the semiconductor apparatus has a metal plating layer formed on each of the first surface electrode and the second surface electrode (The examiner notes that this claim limitation is being interpretated as a product by process limitation with the final product being a metal layer.) Nakata discloses a nickel plating film formed on an emitter electrode by electroless nickel plating (See fig. 6, ref. no. 14 and paragraph 41). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor apparatus of Nagahisa and Narazaki to include electroless plating of the metal layers on the left emitter electrode and the right emitter electrode as taught by Nakata in order to increase uniformity of the metal layers in the semiconductor apparatus . 07-21-aia AIA Claim s 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2007/0114577) in view of Sin et al. (US 2020/0212208) further in view of Nakata et al. (US 2017/0076948) . Regarding Claim 14: Narazaki discloses a manufacturing method for a semiconductor apparatus, comprising: forming a first surface electrode, a second surface electrode and the electroconductive layer with a space from each other in a planar view (forming a left emitter electrode, a right emitter electrode, and a gate wiring are spaced apart from each other, See fig. 6-7, ref. nos. 2, 4, and paragraphs 49-50) by forming and patterning a planar electrode layer on a first main surface of a semiconductor substrate (the left emitter electrode, the right emitter electrode, and the gate wiring layer are formed on a top surface of a semiconductor chip by depositing and patterning an aluminum layer, See figs. 6-7, ref. nos. 1, 2, 4, paragraphs 41 and 51. The examiner notes the aluminum layer patterned to form the left emitter electrode, the right emitter electrode, and the gate wiring layer is a planar layer because one plane will pass through each of the left emitter electrode, the right emitter electrode, and the gate wiring layer. The examiner also notes the aluminum layer is patterned to form the left emitter electrode, the right emitter electrode, and the gate wiring layer because the left emitter electrode, the right emitter electrode, and the gate wiring layer are separate elements.); forming the electroconductive layer (forming the overcoat layer covering the top surface of the semiconductor chip between the left emitter electrode and the gate wiring, the top surface of the semiconductor chip between the right emitter electrode and the gate wiring, and an end portion of each of the left emitter electrode and the right emitter electrode on a side close the gate wiring, See fig. 7, ref. nos. 1, 2, 4, 5, and paragraph 51), the first main surface between the first surface electrode and the second surface electrode, and the insulating layer covering an end portion of each of the first surface electrode and the second surface electrode on a side close to the electroconductive layer; forming a short-circuit prevention layer (forming a polyimide layer covering the overcoat layer between the left emitter electrode and the gate wiring and the overcoat layer between the right emitter electrode and the gate wiring, See fig. 6, ref. no. 2, 4, 5, 13, and paragraph 51) having an insulating property (the polyimide layer is an insulating material, thus, the polyimide layer has an insulating property, See paragraph 48), the short-circuit prevention layer covering the insulating layer between the first surface electrode and the electroconductive layer and the insulating layer between the second surface electrode and the electroconductive layer, having a thickness equal to or larger than a height from a lower end to an upper end of the electroconductive layer (the polyimide layer has a thickness greater than a thickness of the gate wiring layer, See fig. 5, ref. nos. 4, 13, and paragraph 48), and being made of a material different from that of the insulating layer (the polyimide layer is made of polyimide and the overcoat layer is made of insulting material such as silicon dioxide and silicon nitride, See paragraphs 42 and 48); forming a reverse-surface electrode (solder bonding a collector electrode on a bottom surface of the semiconductor, See fig. 2, ref. no. 7 and paragraph 45) on a second main surface which is an opposite surface to the first main surface of the semiconductor substrate. Narazaki does not disclose forming the electroconductive layer using a PVD or CVD method and forming a metal plating layer, after the forming of the short-circuit prevention layer, on the first surface electrode and on the second surface electrode using a plating method by immersing the first surface electrode, the second surface electrode and the short-circuit prevention layer in a plate processing solution. Sin discloses forming the electroconductive layer using a PVD or CVD (depositing a dielectric layer using chemical vapor deposition, See fig. 8 ,ref. no. 210 and paragraph 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for a semiconductor apparatus of Narazaki to include depositing the overcoat layer by chemical vapor deposition as taught by Sin for ease of manufacture of the semiconductor apparatus by using known deposition techniques. The above stated combination of Narazaki and Sin does not disclose forming a metal plating layer, after the forming of the short-circuit prevention layer, on the first surface electrode and on the second surface electrode using a plating method by immersing the first surface electrode, the second surface electrode and the short-circuit prevention layer in a plate processing solution. Nakata discloses forming a metal plating layer (forming a nickel plating film on an emitter electrode, See fig. 6, ref. no. 14 and paragraph 41), after the forming of the short-circuit prevention layer, on the first surface electrode and on the second surface electrode using a plating method by immersing the first surface electrode, the second surface electrode and the short-circuit prevention layer in a plate processing solution (forming a nickel plating film formed on an emitter electrode by immersing the emitter electrode in an electroless Ni plating solution, See fig. 6, ref. no. 14 and paragraph 41). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for a semiconductor apparatus of Narazaki and Sin to include disclose forming a metal plating layer, after the forming of the short-circuit prevention layer, on the first surface electrode and on the second surface electrode using a plating method by immersing the first surface electrode, the second surface electrode and the short-circuit prevention layer in a plate processing solution as taught by Nakata in order to increase uniformity of the metal layers. Regarding Claim 15: Narazaki discloses wherein, in the forming of the short-circuit prevention layer, the insulating layer covering the electroconductive layer is further covered by the short-circuit prevention layer (the polyimide layer covers the overcoat layer coving the gate wiring layer, See fig. 6, ref. nos. 4, 5, 13, and paragraph 51). Regarding Claim 16: Narazaki discloses wherein, in the forming of the short-circuit prevention layer, the insulating layer covering the end portions of the first surface electrode and the second surface electrode is further covered by the short-circuit prevention layer to cause the short-circuit prevention layer to be in contact with the first surface electrode and the second surface electrode (the polyimide layer covers the overcoat layer covering the end portions of the left emitter electrode and the right emitter electrode and the polyimide layer has regions in contact with the left emitter electrode and the right emitter electrode, See fig. 6, ref. nos. 2, 5, 13, and paragraph 51) . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2007/0114577) in view of Sin et al. (US 2020/0212208) in view of Nakata et al. (US 2017/0076948) further in view of Boucher et al. (US 2003/0193545) . Regarding Claim 19: The above stated combination of Narazaki, Sin and Nakata discloses the above stated manufacturing method for a semiconductor device. The above stated combination of Narazaki, Sin, and Nakata does not disclose wherein the short-circuit prevention layer is formed by applying a liquid material using a dispenser and curing the liquid material with light or heat. Boucher discloses wherein the short-circuit prevention layer (dispensed polymer, See fig. 2b, ref. no. 224 and paragraph 31) is formed by applying a liquid material (the polymer is dispensed in a liquid form through a needle dispenser, See paragraph 31) using a dispenser and curing the liquid material with light or heat (the polymer is thermally cured or ultraviolet light cured, See paragraph 31). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for a semiconductor apparatus of Narazaki, Sin and Nakata to include wherein the short-circuit prevention layer is formed by applying a liquid material using a dispenser and curing the liquid material with light or heat as taught by Boucher for ease of manufacture of the semiconductor apparatus through the use of know manufacturing techniques . Allowable Subject Matter 07-43-02 AIA Claim s 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 17-18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for indication of allowable subject matter: with respect to claim 7, the disclosures and illustrations of Narazaki and Nakata as discussed above fail to teach or suggest the recited layout of an emitter electrode, a gate electrode, gate wiring, and a collector electrode. The examiner notes that the disclosures and illustrations of Narazaki and Nakata do not disclose a gate wiring having an electroconductive property formed on the first main surface between the emitter electrode and the gate electrode with a space from the emitter electrode and the gate electrode in a planar view. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Narazaki and Nakata to teach and/or suggest the limitations of claim 7. Therefore, claim 7 includes allowable subject matter. The following is a statement of reasons for indication of allowable subject matter: with respect to claim 8, the disclosures and illustrations of Narazaki and Nakata as discussed above fail to teach or suggest the recited layout of a source electrode, a gate electrode, gate wiring, and a drain electrode. The examiner notes that the disclosures and illustrations of Narazaki and Nakata do not disclose a gate wiring having an electroconductive property formed on the first main surface between the source electrode and the gate electrode with a space from the source electrode and the gate electrode in a planar view. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Narazaki and Nakata to teach and/or suggest the limitations of claim 8. Therefore, claim 8 includes allowable subject matter. The following is a statement of reasons for indication of allowable subject matter: with respect to claim 17, the disclosures and illustrations of Narazaki, Sin, and Nakata as discussed above fail to teach or suggest forming the recited layout of an emitter electrode, a gate electrode, gate wiring, and a collector electrode. The examiner notes that the disclosures and illustrations of Narazaki, Sin, Nakata do not disclose forming an emitter electrode, a gate electrode, and a gate wiring layer with a space from each other in a planar view by forming and patterning a planar electrode layer on a first main surface of a semiconductor substrate. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Narazaki, Sin, and Nakata to teach and/or suggest the limitations of claim 17. Therefore, claim 17 includes allowable subject matter. The following is a statement of reasons for indication of allowable subject matter: with respect to claim 18, the disclosures and illustrations of Narazaki, Sin, and Nakata as discussed above fail to teach or suggest the layout of a source electrode, a gate electrode, gate wiring, and a drain electrode. The examiner notes that the disclosures and illustrations of Narazaki, Sin, and Nakata do not disclose forming a source electrode, a gate electrode, and a gate wiring layer with a space from each other in a planar view by forming and patterning a planar electrode layer on a first main surface of a semiconductor substrate. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Narazaki, Sin, and Nakata to teach and/or suggest the limitations of claim 18. Therefore, claim 18 includes allowable subject matter. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899 /B.S./Examiner, Art Unit 2899 Application/Control Number: 18/685,521 Page 2 Art Unit: 2899 Application/Control Number: 18/685,521 Page 3 Art Unit: 2899 Application/Control Number: 18/685,521 Page 4 Art Unit: 2899 Application/Control Number: 18/685,521 Page 5 Art Unit: 2899 Application/Control Number: 18/685,521 Page 6 Art Unit: 2899 Application/Control Number: 18/685,521 Page 7 Art Unit: 2899 Application/Control Number: 18/685,521 Page 8 Art Unit: 2899 Application/Control Number: 18/685,521 Page 9 Art Unit: 2899 Application/Control Number: 18/685,521 Page 10 Art Unit: 2899 Application/Control Number: 18/685,521 Page 11 Art Unit: 2899 Application/Control Number: 18/685,521 Page 12 Art Unit: 2899 Application/Control Number: 18/685,521 Page 13 Art Unit: 2899 Application/Control Number: 18/685,521 Page 14 Art Unit: 2899 Application/Control Number: 18/685,521 Page 15 Art Unit: 2899 Application/Control Number: 18/685,521 Page 16 Art Unit: 2899 Application/Control Number: 18/685,521 Page 17 Art Unit: 2899 Application/Control Number: 18/685,521 Page 19 Art Unit: 2899 Application/Control Number: 18/685,521 Page 20 Art Unit: 2899 Application/Control Number: 18/685,521 Page 21 Art Unit: 2899 Application/Control Number: 18/685,521 Page 23 Art Unit: 2899 Application/Control Number: 18/685,521 Page 24 Art Unit: 2899 Application/Control Number: 18/685,521 Page 25 Art Unit: 2899
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