Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 9/08/2026 has been entered. Claims 1-21 remain
pending in the application.
Applicants amendments to the claims have overcome the objection to claim 4. Thus, Examiner is withdrawing the objection to claim 4.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues that the addition of the limitation regarding the XRD rocking curve with a FWHM of less than 3000 arcsec of the second III-nitride semiconductor material renders the claims patentable, since none of the references disclose this limitation along with the other limitations. Applicant argues that Hardy, for example, is directed towards the use of ScAlN as an etch stop layer.
Although Examiner agrees with Applicant’s points regarding the this limitation not being disclosed in the other references, it is disclosed in Hardy (see claim rejections below). The issue, in Examiner’s view, is whether a person of ordinary skill in the art would be motivated to combine the teachings of Hardy with Logan to achieve the claimed device. In the view of Examiner, a person of ordinary skill in the art would be so motivated.
Although Hardy’s ScAlN layer is used as an etch stop layer, the idea of having a device with a ScAlN layer with a low FWHM still carries over to other devices. As Examiner notes in the rejection of Claim 1 below, Logan already discloses that the ScAlN is designed to lattice match the GaN layer, and this will reduce the defects in the device. It is known that having a lower FWHM (less than 3000 arcsec) is necessary to ensure the quality of the overall structure of the ScAlN on the GaN. Since a device with a low FWHM number is already disclosed in Hardy, Examiner contends that a person of ordinary skill in the art would find it obvious to ensure that this property is maintained in the device of Logan. Thus, Examiner is rejecting Claim 1 (and the other independent claims) as being obvious in view of Hardy.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US20220262937A1 (Logan) in view of US20180130883A1 (Hardy).
Regarding Claim 1, Logan discloses a device (Fig. 4, el. 100, Para. [0031]), comprising: a substrate (Fig. 4, el. 110, Para. [0031]); and a semiconductor heterostructure (Fig. 4, el. 100, Para. [0031]) supported by the substrate (Fig. 4, Para. [0031]), the semiconductor heterostructure comprising: a first semiconductor layer (Fig. 4, el. 112, Para. [0031]) supported by the substrate (Fig. 4) and comprising a first III-nitride semiconductor material (Para. [0031]); a second semiconductor layer (Fig. 4, el. 116, Para. [0031]) supported by the first semiconductor layer (Fig. 4) and comprising a second III-nitride semiconductor material (Para. [0031]); wherein: the second III-nitride semiconductor material comprises scandium (Para. [0031]); and the first and second layers are nitrogen-polar (Para. [0037]).
Logan does not disclose that the second III-nitride material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-with at half maximum of less than 3000 arc sec.
Hardy discloses a device comprising: a substrate (Fig. 3C, el. 301, Para. [0038]); and a semiconductor heterostructure (Fig. 3C, Para. [0038]) supported by the substrate (Fig. 3C), the semiconductor heterostructure comprising: a first semiconductor layer (Fig. 3A-3C, el. 302, Para. [0038]) and comprising a first III-nitride semiconductor material (Figs. 3A-3C, GaN is a III-nitride semiconductor material); and a second semiconductor layer (Figs. 3A-3C, el. 303, Para. [0038], Although ScAlN is used as an etch-stop layer, it is still a semiconductor layer) supported by the first semiconductor layer (Figs. 3A-3C) and comprising a second III-nitride semiconductor material (Figs. 3A-3C, el. 303, which has AlN as a material), wherein: the second III-nitride semiconductor material comprises scandium (Para. [0038]), the first semiconductor layer is nitrogen-polar (Para. [0040]) and the second semiconductor layer is grown on the first layer (Para. [0040]); and the second III-nitride semiconductor material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-width at half-maximum of less than 3000 arc sec (Para. [0041]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention that the second III-nitride semiconductor material of Logan has a (002) plane X-ray diffraction (XRD) rocking curve with a full-width at half-maximum of less than 3000 arc sec. First, Logan states that the ScAIN lattice-matches to GaN (Para. [0004]), which reduces defects. Hardy shows that epitaxial growth of ScAIN on GaN can be well below 3000 arcsec. Because having a FWHM greater than 3000 arcsec would cause device leakage of the barrier layer (116 in Logan), a person of ordinary skill in the art would find it obvious to process this layer so that it is of high quality (lower FWHM).
Regarding Claim 2, Logan in view of Hardy discloses the device of Claim 1, wherein the semiconductor layer comprises gallium nitride (GaN) (Fig. 4, Para. [0031]).
Regarding Claim 3, Logan in view of Hardy discloses the transistor device of claim 1, wherein the barrier layer comprises scandium aluminum nitride (Fig. 4, Para. [0031]).
Regarding Claim 4, Logan in view of Hardy discloses the transistor device of claim 1, wherein the first semiconductor layer is in contact with the substrate (Fig. 4).
Regarding Claim 6, Logan in view of Hardy discloses the device of claim 1, further comprising a third semiconductor layer disposed between the first and second semiconductor layers (Fig. 4, el. 114, Para. [0031]), wherein the third semiconductor layer comprises a third III-nitride semiconductor material differing from the first III-nitride semiconductor material (Para. [0032], where the layer 114 can be a graded rare-earth II-nitride alloy, whereas the first III-nitride material is GaN).
Regarding Claim 8, Logan in view of Hardy discloses the device of claim 1, wherein the first and second semiconductor layers are lattice matched (Para. [0004]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy.
Regarding Claim 5, Logan in view of Hardy discloses the device of claim 1.
Logan, in Fig. 4, does not disclose that the second semiconductor layer is in contact with the first semiconductor layer.
However, Logan, in Fig. 5, discloses that the second semiconductor layer may be in contact with the first semiconductor layer (Para. [0041] – “An optional charge mitigation transition layer 216 can then be grown onto buffer layer 214”).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to remove the charge mitigation transition layer to reduce the complexity and manufacturing difficulty of the device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy.
Regarding Claim 7, Logan in view of Hardy discloses the device of Claim 1, where the third semiconductor layer can be a graded rare-earth III-nitride alloy (para. [0044])
Logan in view of Hardy does not disclose the third semiconductor layer comprises aluminum nitride.
However, Hardy discloses a possible third semiconductor layer which may comprise AlN (Para. [0034]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to make the third semiconductor layer of Logan AlN. This would be a simple substitution of one known element (AlN) for another (a rare earth III nitride alloy) to yield predictable results (a device with a third semiconductor layer made of AlN)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy and US20190237570A1 (Beam).
Regarding Claim 9, Logan in view of Hardy discloses the device of Claim 1.
Logan in view of Hardy does not disclose that the first and second semiconductor layers are lattice mismatched.
Beam discloses a device (Fig. 2, el. 32, Para. [0025]) with a buffer layer (Fig. 2, el. 36) and a barrier layer over the buffer layer (Fig. 2, el. 38, Para. [0025]), wherein the buffer layer comprises GaN (Fig. 2, Para. [0025]), and the barrier layer comprises ScAlGaN (Fig. 2, Para. [0025]), and wherein the buffer and barrier layers may be lattice mismatched (Para. [0026]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to make the first and second semiconductor layers of Logan lattice mismatched, as disclosed by Beam. As disclosed by Beam, this has the benefit of providing a relatively higher sheet charge density while providing the same reliability as modern HEMT devices (Para. [0026]).
Claims 10 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy.
Regarding Claim 10, Logan discloses a transistor device (Fig. 4, el. 100, Para. [0031]), comprising: a substrate (Fig. 4, el. 110, Para. [0031]); a buffer layer (Fig. 4, el. 112, Para. [0031]) supported by the substrate (Fig. 4) and comprising a first III-nitride semiconductor material (Para. [0031]); a barrier layer (Fig. 4, el. 116, Para. [0031]) supported by the buffer layer (Fig. 4) and comprising a second III-nitride semiconductor material (Para. [0031]); and a channel layer (Fig. 4, el. 118, Para. [0031]) supported by the barrier layer (Fig. 4) and comprising a compound semiconductor material (Para. [0033]), wherein: the second III-nitride semiconductor material comprises scandium (Para. [0031]); and the buffer and barrier layers are nitrogen-polar (Para. [0037]).
Logan does not disclose that the second III-nitride material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-with at half maximum of less than 3000 arc sec.
Hardy discloses a device comprising: a substrate (Fig. 3C, el. 301, Para. [0038]); and a semiconductor heterostructure (Fig. 3C, Para. [0038]) supported by the substrate (Fig. 3C), the semiconductor heterostructure comprising: a first semiconductor layer (Fig. 3A-3C, el. 302, Para. [0038]) and comprising a first III-nitride semiconductor material (Figs. 3A-3C, GaN is a III-nitride semiconductor material); and a second semiconductor layer (Figs. 3A-3C, el. 303, Para. [0038], Although ScAlN is used as an etch-stop layer, it is still a semiconductor layer) supported by the first semiconductor layer (Figs. 3A-3C) and comprising a second III-nitride semiconductor material (Figs. 3A-3C, el. 303, which has AlN as a material), wherein: the second III-nitride semiconductor material comprises scandium (Para. [0038]), the first semiconductor layer is nitrogen-polar (Para. [0040]) and the second semiconductor layer is grown on the first layer (Para. [0040]); and the second III-nitride semiconductor material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-width at half-maximum of less than 3000 arc sec (Para. [0041]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention that the second III-nitride semiconductor material of Logan has a (002) plane X-ray diffraction (XRD) rocking curve with a full-width at half-maximum of less than 3000 arc sec. First, Logan states that the ScAIN lattice-matches to GaN (Para. [0004]), which reduces defects. Hardy shows that epitaxial growth of ScAIN on GaN can be well below 3000 arcsec. Because having a FWHM greater than 3000 arcsec would cause device leakage of the barrier layer (116 in Logan), a person of ordinary skill in the art would find it obvious to process this layer so that it is of high quality (lower FWHM).
Regarding Claim 12, Logan in view of Hardy discloses the transistor device of claim 10, wherein the compound semiconductor material comprises the first III-nitride semiconductor material (Fig. 4, where both the buffer layer and channel layer are made of GaN).
Regarding Claim 13, Logan in view of Hardy discloses the transistor device of Claim 10, wherein the buffer layer comprises gallium nitride (GaN) (Fig. 4, Para. [0031]).
Regarding Claim 14, Logan of Hardy discloses the transistor device of claim 10, wherein the barrier layer comprises scandium aluminum nitride (Fig. 4, Para. [0031]).
Regarding Claim 15, Logan in view of Hardy discloses the transistor device of claim 10, wherein the buffer layer is in contact with the substrate (Fig. 4).
Regarding Claim 16, Logan in view of Hardy discloses the transistor device of claim 10, further comprising a further semiconductor layer disposed between the buffer an barrier layers (Fig. 4, el. 114, Para. [0031]), wherein the further semiconductor layer comprises a third III-nitride semiconductor material differing from the first III-nitride semiconductor material (Para. [0032], where the layer 114 can be a graded rare-earth II-nitride alloy, whereas the first III-nitride material is GaN).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy and Beam.
Regarding Claim 11, Logan in view of Hardy discloses the transistor device of Claim 10.
Logan does not disclose that the first III-nitride semiconductor material and the second III-nitride semiconductor material are lattice mismatched.
Beam discloses a device (Fig. 2, el. 32, Para. [0025]) with a buffer layer (Fig. 2, el. 36) and a barrier layer over the buffer layer (Fig. 2, el. 38, Para. [0025]), wherein the buffer layer comprises GaN (Fig. 2, Para. [0025]), and the barrier layer comprises ScAlGaN (Fig. 2, Para. [0025]), and wherein the buffer and barrier layers may be lattice mismatched (Para. [0026]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to make the first and second III-nitride material of Logan lattice mismatched, as disclosed by Beam. As disclosed by Beam, this has the benefit of providing a relatively higher sheet charge density while providing the same reliability as modern HEMT devices (Para. [0026]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy.
Regarding Claim 17, Logan in view of Hardy discloses the device of Claim 16, where the third semiconductor layer can be a graded rare-earth III-nitride alloy (para. [0044])
Logan in view of Hardy does not disclose the third semiconductor layer comprises aluminum nitride.
However, Hardy discloses a possible third semiconductor layer which may comprise AlN (Para. [0034]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to make the third semiconductor layer of Logan AlN. This would be a simple substitution of one known element (AlN) for another (a rare earth III nitride alloy) to yield predictable results (a device with a third semiconductor layer made of AlN)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Logan in view of Hardy and Beam.
Regarding Claim 18, Logan discloses a transistor device (Fig. 4, el. 100, Para. [0031]), comprising: a substrate (Fig. 4, el. 110, Para. [0031]); a buffer layer (Fig. 4, el. 112, Para. [0031]) supported by the substrate (Fig. 4) and comprising a first III-nitride semiconductor material (Para. [0031]); a barrier layer (Fig. 4, el. 116, Para. [0031]) supported by the buffer layer (Fig. 4) and comprising a second III-nitride semiconductor material (Para. [0031]); and a channel layer (Fig. 4, el. 118, Para. [0031]) supported by the barrier layer (Fig. 4) and comprising a compound semiconductor material (Para. [0033]), wherein: the second III-nitride semiconductor material comprises scandium (Para. [0031]).
Logan does not disclose that the first III-nitride semiconductor material and the second III-nitride semiconductor material are lattice mismatched, and does not disclose that the second III-nitride material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-with at half maximum of less than 3000 arc sec.
Beam discloses a device (Fig. 2, el. 32, Para. [0025]) with a buffer layer (Fig. 2, el. 36) and a barrier layer over the buffer layer (Fig. 2, el. 38, Para. [0025]), wherein the buffer layer comprises GaN (Fig. 2, Para. [0025]), and the barrier layer comprises ScAlGaN (Fig. 2, Para. [0025]), and wherein the buffer and barrier layers may be lattice mismatched (Para. [0026]).
Hardy discloses a device comprising: a substrate (Fig. 3C, el. 301, Para. [0038]); and a semiconductor heterostructure (Fig. 3C, Para. [0038]) supported by the substrate (Fig. 3C), the semiconductor heterostructure comprising: a first semiconductor layer (Fig. 3A-3C, el. 302, Para. [0038]) and comprising a first III-nitride semiconductor material (Figs. 3A-3C, GaN is a III-nitride semiconductor material); and a second semiconductor layer (Figs. 3A-3C, el. 303, Para. [0038], Although ScAlN is used as an etch-stop layer, it is still a semiconductor layer) supported by the first semiconductor layer (Figs. 3A-3C) and comprising a second III-nitride semiconductor material (Figs. 3A-3C, el. 303, which has AlN as a material), wherein: the second III-nitride semiconductor material comprises scandium (Para. [0038]), the first semiconductor layer is nitrogen-polar (Para. [0040]) and the second semiconductor layer is grown on the first layer (Para. [0040]); and the second III-nitride semiconductor material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-width at half-maximum of less than 3000 arc sec (Para. [0041]).
First, it would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to make the first and second III-nitride material of Logan lattice mismatched, as disclosed by Beam. As disclosed by Beam, this has the benefit of providing a relatively higher sheet charge density while providing the same reliability as modern HEMT devices (Para. [0026]).
Second, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention that the second III-nitride semiconductor material of Logan has a (002) plane X-ray diffraction (XRD) rocking curve with a full-width at half-maximum of less than 3000 arc sec. First, Logan states that the ScAIN lattice-matches to GaN (Para. [0004]), which reduces defects. Hardy shows that epitaxial growth of ScAIN on GaN can be well below 3000 arcsec. Because having a FWHM greater than 3000 arcsec would cause device leakage of the barrier layer (116 in Logan), a person of ordinary skill in the art would find it obvious to process this layer so that it is of high quality (lower FWHM).
Claims 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Appl. Phys. Lett. 116, 151903 (2020) (Wang) in view of US20220109064A1 (Arkun).
Regarding Claim 19, Wang discloses a method of fabricating a heterostructure (pg. 116, 151903-2, Para. [2] – “In this study, ScAlN samples were grown on GaN and AlN templates…”), the method comprising: a first semiconductor layer comprising a first III-nitride semiconductor material (pg. 116, 151903-2, Para. [2] – “…samples were grown on GaN…”), the first III-nitride semiconductor material being supported by a substrate (pg. 116, 151903-2, Para. [2] – “…GaN and AlN templates on sapphire…”); and after growing the first semiconductor layer, growing epitaxially a second semiconductor layer of the heterostructure (pg. 116, 151903-2, Para. [4] – “During the epitaxy of ScAlN…”) such that the second semiconductor layer is supported by the first semiconductor layer (pg. 116, 151903-2, Para. [4] – “We have first studied the growth of ScAlN on GaN…”), the second semiconductor layer comprising a second III-nitride semiconductor material (pg. 116, 151903-2, Para. [4]), wherein the second III-nitride semiconductor material comprises scandium (pg. 116, 151903-2, Para. [4]),wherein the second III-nitride material has a (002) plane X-ray diffraction (XRD) rocking curve with a full-with at half maximum of less than 3000 arc sec (see Fig. 1A).
Wang does not disclose that the first semiconductor layer was epitaxially grown, does not disclose that the first and second layers are nitrogen polar.
Arkun discloses a method of fabricating a heterostructure (Figs. 13A-13I, Para. [0050] – the method forms device 1100), where a first semiconductor layer and a second semiconductor layer are epitaxially grown (Para. [0049]), and the first and second semiconductor layers are nitrogen-polar (Para. [0047]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to grow the first semiconductor layer epitaxially, as in Arkun, as the GaN serves as a template for the ScAlN layer, which is epitaxially grown. Further, it would have been obvious to make the first and second semiconductor layers N-polar, as in Arkun, as this would have the benefit of forming vertical transistors, among other benefits.
Regarding Claim 20, Wang in view of Arkun discloses the method of claim 19, wherein growing epitaxially the second semiconductor layer is implemented under nitrogen-rich conditions (pg. 116, 151903-2, Para. [2] – “Therefore, nitrogen-rich conditions were chosen for the growth of ScAlN in this work”).
Regarding Claim 21, Wang in view of Arkun discloses the method of claim 19, wherein growing epitaxially the second semiconductor layer is implemented at a growth temperature falling in a range from about 600 degrees Celsius to about 900 degrees Celsius (pg. 116, 151903-2, Para. [4] – The growth conditions …and TG in the range of 400-900 degrees Celsius).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights