DETAILED ACTION
This action is responsive to the following communications: the Response to Election/Restriction filed on January 9, 2026, the Foreign Priority papers retrieved on August 26, 2021 and the Information Disclosure Statements filed on February 26, 2024 and September 17, 2025.
Claims 1-6 and 9-10 are pending. Claims 7-8 are canceled. Claims 11-22 are withdrawn due to an Election/Restriction Requirement. Claims 1, 11 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions Group II and III, there being no allowable generic or linking claim. Applicant’s election without traverse of Group I (Claims 1-6 and 9-10) in the reply filed on January 9, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 9640252).
Regarding independent claim 1, Yang discloses a flash memory array [see Fig. 1] comprising:
a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction [see Fig. 1, col. 2, lines 19-29];
a plurality of word line sets extending in the row direction [see Fig. 1]; and
a plurality of bit line sets extending in the column direction [see Fig. 1],
wherein a flash memory cell pair is disposed at an intersection of the word line set and the bit line set, and the flash memory cell pair includes a first flash memory cell [Fig. 1: 100] and a second flash memory cell [Fig. 1: 200] adjacent in the row direction and sharing the same bit line set [col. 2, lines 30-44].
Regarding claim 2, Yang discloses wherein each of the first flash memory cell [Fig. 2: 100] and the second flash memory cell [Fig. 2: 200] includes a first storage transistor [Fig. 2: CG0], a selection transistor [Fig. 2: WL], and a second storage transistor [Fig. 2: CG1] sequentially connected in series in the column direction [see Fig. 2 with respect to Fig. 1, col. 5, lines 55-67 and col. 6, lines 1-12], and
wherein, in each of the first flash memory cell and the second flash memory cell, a source region of the first storage transistor is connected to a first electrode of the flash memory cell, and a drain region of the second storage transistor is connected to a second electrode of the flash memory cell [see Fig. 2 with respect to Fig. 1, col. 2, lines 21-35].
Regarding claim 3, Yang discloses wherein each bit line set includes a first bit line, a middle bit line, and a second bit line, the first bit line is connected to the first electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the middle bit line is connected to the second electrode of the first flash memory cell and the first electrode of the second flash memory cell [see Fig. 1, the source of the first split-gate flash memory unit 100 is connected with a first bit line BL0, the source of the second split-gate flash memory unit 200 is connected with a second bit line BL2, the drain of the first split-gate flash memory unit 100 is connected with the drain of the second split-gate flash memory unit 200 and a third bit line BL1. A person of ordinary skill in the art would have found it obvious to provide an alternative way of connecting the bit lines with the electrodes of the cell that presented by claim 3].
Regarding claim 4, Yang discloses wherein each bit line set includes a first bit line [Fig. 1: BL0], a middle bit line [Fig. 1: BL1], and a second bit line [Fig. 1: BL2], the first bit line [Fig. 1: BL0] is connected to the second electrode [Fig. 1: B] of the first flash memory cell [Fig. 1: 100] of the flash memory cell pair, the second bit line [Fig. 1: BL2] is connected to the second electrode [Fig. 1: B] of the second flash memory cell [Fig. 1: 200] of the flash memory cell pair, and the middle bit line [Fig. 1: BL1] is connected to the first electrode [Fig. 1: A] of the first flash memory cell and the first electrode of the second flash memory cell [col. 2, lines 21-35].
Regarding claim 5, Yang discloses wherein each word line set includes a first control line [Fig. 1: CG0], a word line [Fig. 1: WL] and a second control line [Fig.1: CG2] extending along the row direction, the first control line is connected to a gate electrode of the first storage transistor, the word line is connected to a gate electrode of the selection transistor, and the second control line is connected to a gate electrode of the second storage transistor [the plurality of first split-gate flash memory units 100 and the plurality of second split-gate flash memory units 200 share the word line WL, the first control gate line CG0 and the second control gate line CG1, col. 2, lines 47-51].
Regarding claim 6, Yang discloses wherein two first control lines adjacent in the column direction are connected together by a first common control line, and two second control lines adjacent in the column direction are connected together by a second common control line [see Examiner Markup Yang’s Figure 1].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 9640252) as applied to claim 3 above, in view of Kuo et al. (US 6421267).
Regarding claim 9, Yang teaches the limitations with respect to claim 3.
However, Yang is silent with respect to the middle bit line is formed of a first metal layer and the first bit line and the second bit line are formed of a second metal layer different from the first metal layer.
Kuo et al. teach the middle bit line is formed of a first metal layer and the first bit line and the second bit line are formed of a second metal layer different from the first metal layer [see Fig. 2, adjacent bit lines are located in different metal layers, col. 3, lines 56-57. The first bit line BL1 and the third bit line BL3 are located in the first metal layer, and the second bit line BL2 is located in the second metal layer, col. 4, lines 2-12].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Kuo et al. to the teaching of Yang such that modifying Yang’s split gate flash memory array to implement the different metal layer bit line placement as taught by Kuo et al. to reduce the coupling effect between bit lines and improve the performance of memory [see Kuo et al.’s col. 2, lines 61-67].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 9640252) in view of Kuo et al. (US 6421267) as applied to claim 9 above and further in view of Nakagawa et al. (US 604592).
Regarding claim 10, Yang in combination with Kuo et al. teach the limitations with respect to claim 9.
However, Yang in combination with Kuo et al. are silent with respect to wherein the middle bit line includes a first portion extending in the column direction and a second portion extending in the row direction, and the first bit line and the second bit line extend in the column direction.
Nakagawa et al. teach wherein the middle bit line includes a first portion extending in the column direction and a second portion extending in the row direction, and the first bit line and the second bit line extend in the column direction [see Fig. 10 with respect to Fig. 7, the main bit lines 50 ran zigzag in the column direction connecting the buried local bit lines 18a and 18e in two adjacent columns of memory cell blocks alternately, col. 4, lines 53-56. Five elongated "buried" diffusion regions 18a-18e are formed on a semiconductor substrate (not shown) in parallel in the column direction, col. 4, lines 5-7].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Nakagawa et al. to the teaching of Yang in combination with Kuo et al. such that modifying the split gate flash memory array of Yang in combination with Kuo et al. to implement the layout of bit lines as taught by Nakagawa et al. to reduce the memory cell area [see Nakagawa et al.’s col. 4, lines 56-61].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825