DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6, 10-12 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US PGPub 2019/0079699, hereafter “Lee,” in view of Lim et al., US PGPub 2018/0144786, hereafter “Lim.”
With respect to claim 1, Lee teaches a memory controller, comprising:
a data interface, comprising at least two separate data signals, to communicate data with at least two separate memory devices (fig. 10a: memory groups 560_1, 560_2), respectively (par. 0016: the method comprising: forming a memory system as part of a semiconductor package that includes one or more memory chips having a memory cell array, a memory controller, and a buffer chip for routing transmission/reception signals between the one or more memory chips and the memory controller; and performing, by the memory controller, training operations for the buffer chip and subsequently performing, under control of the memory controller, training operations for the one or more memory chips using the buffer chip. par. 0010: The first training operations, second training operations and third training operations comprise generation of timing compensation information for one or more of a read training operation, and a write training operation.); and
a data strobe interface to transmit a first data strobe signal providing, to the at least two separate memory devices during write operations (fig. 4a, DQS'; par. 0039: signal transmitted via a data DQ line between the memory controller 120 and the memory module MM or a data DQ line between the buffer device 140 and each of the memory devices 160 is referred to as a data signal. Also, a signal transmitted via a data strobe DQS line between the memory controller 120 and the memory module MM or a data strobe DQS line between the buffer device 140 and each of the memory devices 160 is referred to as a data strobe signal), a first timing for the at least two separate data signals (par. 0050: firstly, the alignment of signals between the memory controller 120 and the buffer device 140 (for example, alignment between data signals and data strobe signals) are optimized. Thus, the memory controller 120 may perform training operations for the buffer device 140 before starting the training operations for the memory devices 160 using the training block TB, and may determine a degree of timing compensation for signals transmitted by the memory controller 120 to the buffer device 140 and a degree of timing compensation for signals received from the buffer device 140.) and to receive, from a first memory device of the at least two separate memory devices (fig. 10a: memory groups 560_1, 560_2), a second data strobe signal (fig. 4d, par. 0076: The delay adjusting circuit 224 (in the memory controller 220) may generate a fourth timing compensation information TCI4 based on the fourth comparison result COM_R4. The fourth timing compensation information TCI4 that is generated as a result of performing read training operations for the memory device 260, may be, for example, information indicating a degree of optimum timing compensation for at least one of a data signal and a data strobe signal, which are transmitted by the buffer device 240 to the memory device 260. In an example, the buffer device 240 may compensate for timing for the data strobe signal transmitted to the memory device 260 by referring to the fourth timing compensation information TCI4 and then may transmit the compensated data strobe signal and the data signal to the memory device 260, thereby performing a write operation.) providing, to the memory controller, a second timing for the at least two separate data signals (par. 0050: firstly, the alignment of signals between the memory controller 120 and the buffer device 140 (for example, alignment between data signals and data strobe signals) are optimized. Thus, the memory controller 120 may perform training operations for the buffer device 140 before starting the training operations for the memory devices 160 using the training block TB, and may determine a degree of timing compensation for signals transmitted by the memory controller 120 to the buffer device 140 and a degree of timing compensation for signals received from the buffer device 140.).
Lee fails to teach that the first data strobe signal is directly provided to the at least two separate memory devices, and directly receiving a second data strobe signal, as Lee shows a buffer device in between the memory controller and the memory.
Lim teaches a data strobe interface to transmit a first data strobe signal directly providing, to the at least two separate memory devices during write operations, a first timing for the at least two separate data signals and to directly receive, from a first memory device of the at least two separate memory devices, a second data strobe signal providing, to the memory controller, a second timing for the at least two separate data signals (pars. 117-118 and fig. 13C, each memory device 400a-400h provides and receives to and from memory controller 500C, data signals DQ and data strobe signals DQS).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Lim before him before the earliest effective filing date, to modify the memory system of Lee with the memory system of Lim, as it would be obvious to try. Lim shows multiple configurations for interfacing a memory with a controller (figures 13A-13C). These include a path between a controller, a buffer and the memory; a path between a controller and a dedicated buffer and a memory; and a path directly between the controller and memory. Being that there are only a limited number of options, having a direct connection would be obvious to try.
With respect to claim 2, Lee and Lim teach all limitations of the parent claim. Lee further teaches the memory controller of claim 1, further comprising:
circuitry to configure the first memory device to provide the second data strobe signal to the memory controller (fig. 4d, par. 0076: The delay adjusting circuit 224 (in the memory controller 220) may generate a fourth timing compensation information TCI4 based on the fourth comparison result COM_R4. The fourth timing compensation information TCI4 that is generated as a result of performing read training operations for the memory device 260, may be, for example, information indicating a degree of optimum timing compensation for at least one of a data signal and a data strobe signal, which are transmitted by the buffer device 240 to the memory device 260. In an example, the buffer device 240 may compensate for timing for the data strobe signal transmitted to the memory device 260 by referring to the fourth timing compensation information TCI4 and then may transmit the compensated data strobe signal and the data signal to the memory device 260, thereby performing a write operation.).
With respect to claim 3, Lee and Lim teach all limitations of the parent claim. Lee further teaches the memory controller of claim 1, wherein the first data strobe signal is transmitted during a write operation (par. 0072: The training block TB may provide a data strobe signal DQS having a high frequency to the memory device 260 via a data strobe signal line. In an example, the data strobe signal DQS may have the same frequency as that of a data strobe signal used in a write operation.).
With respect to claim 4, Lee and Lim teach all limitations of the parent claim. Lee further teaches the memory controller of claim 2, wherein the second data strobe signal is transmitted during a read operation (par. 0071: In an example, when receiving the data signal and the data strobe signal from the memory device 260 the buffer device 240 may compensate for the timing of the data strobe signal by referring to the third timing compensation information TCI3 and then may perform a read operation.).
With respect to claim 6, Lee and Lim teach all limitations of the parent claim. Lee further teaches the memory controller of claim 1, further comprising:
circuitry to configure the at least two separate memory devices to calibrate skew between the first data strobe signal and the at least two separate data signals (par. 0005: to compensate for timing for at least one of a data signal (or a DQ signal) transmitted via a data DQ line and a data strobe signal (or a DQS signal) transmitted via a data strobe DQS line, to establish an optimum alignment condition and to control a memory operation).
With respect to claim 10, Lee teaches a memory controller, comprising:
a data strobe interface to transmit a first data strobe signal to a plurality of memory devices (fig. 10a: memory groups 560_1, 560_2. par. 0016: the method comprising: forming a memory system as part of a semiconductor package that includes one or more memory chips having a memory cell array, a memory controller, and a buffer chip for routing transmission/reception signals between the one or more memory chips and the memory controller; and performing, by the memory controller, training operations for the buffer chip and subsequently performing, under control of the memory controller, training operations for the one or more memory chips using the buffer chip. par. 0010: The first training operations, second training operations and third training operations comprise generation of timing compensation information for one or more of a read training operation, and a write training operation.); and
a data interface to transmit, to the plurality of memory devices (fig. 4a, DQS'; par. 0039: signal transmitted via a data DQ line between the memory controller 120 and the memory module MM or a data DQ line between the buffer device 140 and each of the memory devices 160 is referred to as a data signal. Also, a signal transmitted via a data strobe DQS line between the memory controller 120 and the memory module MM or a data strobe DQS line between the buffer device 140 and each of the memory devices 160 is referred to as a data strobe signal), first data timed according to the first data strobe signal (par. 0050: firstly, the alignment of signals between the memory controller 120 and the buffer device 140 (for example, alignment between data signals and data strobe signals) are optimized. Thus, the memory controller 120 may perform training operations for the buffer device 140 before starting the training operations for the memory devices 160 using the training block TB, and may determine a degree of timing compensation for signals transmitted by the memory controller 120 to the buffer device 140 and a degree of timing compensation for signals received from the buffer device 140.).
Lee and Lim fail to teach that the data strobe interface to transmit a first data strobe signal to a plurality of memory devices via a single pair of signal conductors. Lim teaches:
a data strobe interface to directly transmit a first data strobe signal to a plurality of memory devices via a single pair of signal conductors (par. 117 and fig. 13c, the data strobe signal is provided to the memory devices 400a-400h through a single pair of signal conductors 210).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Lim before him before the earliest effective filing date, to modify the memory system of Lee with the memory system of Lim, as it would be obvious to try. Lim shows multiple configurations for interfacing a memory with a controller (figures 13A-13C). These include a path between a controller, a buffer and the memory; a path between a controller and a dedicated buffer and a memory; and a path directly between the controller and memory. Being that there are only a limited number of options, having a direct connection would be obvious to try.
With respect to claim 11, Lee and Lim teach the limitations of the parent claim. Lee further teaches the memory controller of claim 10, wherein the data strobe interface is to receive, and from a first memory device of the plurality of memory devices, a second data strobe signal (fig. 4d, par. 0076: The delay adjusting circuit 224 (in the memory controller 220) may generate a fourth timing compensation information TCI4 based on the fourth comparison result COM_R4. The fourth timing compensation information TCI4 that is generated as a result of performing read training operations for the memory device 260, may be, for example, information indicating a degree of optimum timing compensation for at least one of a data signal and a data strobe signal, which are transmitted by the buffer device 240 to the memory device 260. In an example, the buffer device 240 may compensate for timing for the data strobe signal transmitted to the memory device 260 by referring to the fourth timing compensation information TCI4 and then may transmit the compensated data strobe signal and the data signal to the memory device 260, thereby performing a write operation.), and the data interface is to receive, from the plurality of memory devices, second data timed according to the second data strobe signal (par. 0050: firstly, the alignment of signals between the memory controller 120 and the buffer device 140 (for example, alignment between data signals and data strobe signals) are optimized. Thus, the memory controller 120 may perform training operations for the buffer device 140 before starting the training operations for the memory devices 160 using the training block TB, and may determine a degree of timing compensation for signals transmitted by the memory controller 120 to the buffer device 140 and a degree of timing compensation for signals received from the buffer device 140.). Prakash teaches receiving via the single pair of signal conductors (par. 56, as discussed above).
With respect to claim 12, Lee and Lim teach the limitations of the parent claim. Lee further teaches the memory controller of claim 11, further comprising: first circuitry to configure the first memory device of the plurality of memory devices to provide the second data strobe signal to the memory controller (fig. 4d, par. 0076: The delay adjusting circuit 224 (in the memory controller 220) may generate a fourth timing compensation information TCI4 based on the fourth comparison result COM_R4. The fourth timing compensation information TCI4 that is generated as a result of performing read training operations for the memory device 260, may be, for example, information indicating a degree of optimum timing compensation for at least one of a data signal and a data strobe signal, which are transmitted by the buffer device 240 to the memory device 260. In an example, the buffer device 240 may compensate for timing for the data strobe signal transmitted to the memory device 260 by referring to the fourth timing compensation information TCI4 and then may transmit the compensated data strobe signal and the data signal to the memory device 260, thereby performing a write operation.). Prakash teaches via the single pair of signal conductors (par. 56, as discussed above).
Claims 16-18 are a method that corresponds to claims 10-12 and are rejected using similar logic.
Claim(s) 5, 9, 13-15 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Lim as applied to claims 1-2, 10-12, and 16-18 above, in view of Prakash et al., US PGPub 2014/0307514, hereafter “Prakash.”.
With respect to claim 5, Lee and Lim teach the limitations of the parent claim, but fail to teach wherein a second memory device of the at least two separate memory devices presents an on-die termination impedance to the second data strobe signal while the first memory device is transmitting the second data strobe signal. Prakash teaches the memory controller of claim 2, wherein a second memory device of the at least two separate memory devices presents an on-die termination impedance to the second data strobe signal while the first memory device is transmitting the second data strobe signal (par. 0056: however when DQS is not being driven by the respective DDR3 memory module 16 (prior to the preamble portion or after the postamble portion) termination of the DQS input pad at the bytelane 18 (discussed in more detail below) mean that the DQS input pad voltage is kept near a mid rail value and the logical data strobe signal generated can give an unknown result.).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Lim and Prakash before him before the earliest effective filing date, to modify the memory controller of Lee and Lim with the memory controller of Prakash, in order to improve signal integrity while operating a memory system at high frequency, as taught by Prakash in par. 52.
With respect to claim 9, Lee and Lim teach the limitations of the parent claim, but fail to teach circuitry to configure an on-die termination impedance of at least two separate memory devices. Prakash teaches the memory controller of claim 1, further comprising:
circuitry to configure an on-die termination impedance of at least two separate memory devices (fig. 4,7; par. 0059: To avoid stray noise during this tri-state condition, on-die-termination (ODT) is enabled prior to the training process being carried out and remains on throughout).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Lim and Prakash before him before the earliest effective filing date, to modify the memory controller of Lee and Lim with the memory controller of Prakash, in order to improve signal integrity while operating a memory system at high frequency, as taught by Prakash in par. 52.
With respect to claim 13, Lee and Lim teach the limitations of the parent claim, but fail to teach second circuitry to configure an on-die termination impedance of the plurality of memory devices. Prakash further teaches the memory controller of claim 12, further comprising: second circuitry to configure an on-die termination impedance of the plurality of memory devices (fig. 4,7; par. 0059: To avoid stray noise during this tri-state condition, on-die-termination (ODT) is enabled prior to the training process being carried out and remains on throughout).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Lim and Prakash before him before the earliest effective filing date, to modify the memory controller of Lee and Lim with the memory controller of Prakash, in order to improve signal integrity while operating a memory system at high frequency, as taught by Prakash in par. 52.
With respect to claim 14, Lee, Lim and Prakash teach the limitations of the parent claim. Prakash further teaches the memory controller of claim 13, wherein a second memory device of the plurality of memory devices presents the on-die termination impedance while the first memory device of the plurality of memory devices is transmitting the second data strobe signal (par. 0056: however when DQS is not being driven by the respective DDR3 memory module 16 (prior to the preamble portion or after the postamble portion) termination of the DQS input pad at the bytelane 18 (discussed in more detail below) mean that the DQS input pad voltage is kept near a mid rail value and the logical data strobe signal generated can give an unknown result.). Prakash teaches the single pair of signal conductors (par. 56, as discussed above).
With respect to claim 15, Lee, Lim and Prakash teach the limitations of the parent claim. Lee further teaches the memory controller of claim 14, further comprising: third circuitry to configure the plurality of memory devices to calibrate skew between the first data strobe signal and the first data (par. 0005: to compensate for timing for at least one of a data signal (or a DQ signal) transmitted via a data DQ line and a data strobe signal (or a DQS signal) transmitted via a data strobe DQS line, to establish an optimum alignment condition and to control a memory operation).
Claims 19-20 are a method that corresponds to claims 13-14 and are rejected using similar logic.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Lim as applied to claim 1 above, in view of Ahn et al., US PGPub 2006/0280024, hereafter “Ahn.”.
With respect to claim 7, Lee and Lim teach all limitations of the parent claim, but fail to disclose an H-tree routing topology. Ahn teaches the memory controller of claim 1, wherein the data strobe interface is to communicate the first data strobe signal and the second data strobe signal with the at least two separate memory devices via an H-tree signal routing topology (par. 17, the H-tree topology for the memory devices).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Lim, and Ahn before him before the earliest effective filing date, to modify the memory of Lee and Lim with the memory of Ahn, in order to implement an H-tree topology, which attempts to minimize transmission related distortion of the signal by balancing respective signal line impedances, as taught by Ahn in par. 17.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Lim as applied to claim 1 above, in view of Leslie, US PGPub 2022/0076721.
With respect to claim 8, Lee and Lim teach all limitations of the parent claim, but fail to disclose a start signal routing topology. Leslie teaches the memory controller of claim 1, wherein the data strobe interface is to communicate the first data strobe signal and the second data strobe signal with the at least two separate memory devices via a star signal routing topology (par. 83, four memory devices are arranged in a star 4 topology).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Lim and Leslie before him before the earliest effective filing date, to modify the memory of Lee and Lim with the memory of Leslie, in order to provide high speed memory access while preserving command/address signal integrity with a routing complexity repeatable and achievable on DIMM memory chips through use of a star connection topology, as taught by Leslie in par. 14.
Response to Arguments
Applicant's arguments filed 10/16/2025 have been fully considered but they are not persuasive. Applicant’s arguments on pages 7-8, with respect to independent claims 1, 10 and 16, are directed towards the amended limitation feature of a controller directly providing and directly receiving data signals, as Lee has an intermediate component in the signaling path. Similarly, Applicant argues on pages 8-9 that Prakash fails to teach this feature. These arguments are moot, as the new Lim reference has been supplied to teach this limitation. Further, the examiner is no longer relying on Prakash to teach any element of independent claim 10 or 16.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132