DETAILED ACTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (20200411758).
Regarding Claim 1, in Figs. 18, 19 and 20, Lin et al. discloses a method for manufacturing a semiconductor device, comprising: depositing a first dielectric layer 414/416 material on a semiconductor substrate, and etching the first dielectric layer material to form a trench corresponding to each via 404b in the semiconductor substrate in a first dielectric layer, the via being filled with a metal material; depositing a bottom electrode material 108 in the trench, and etching the bottom electrode material to form a bottom electrode covering a bottom of the trench; depositing a resistive layer 110 material to form a resistive layer covering an upper surface of the bottom electrode and a sidewall of the trench 1802; and depositing a top electrode material 106 in a groove of the resistive layer (please note that resistive layer is U shaped and hence inherently has a groove), wherein the groove is filled with the top electrode material 106 to form a top electrode wherein the top electrode is arranged in the groove and fills the groove (again all these layers are U shaped and hence inherent presence of groove).
Regarding Claim 2, performing planarization, wherein an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 108 and an upper surface of the top electrode 106 in the trench.
Regarding Claim 3, a semiconductor substrate, a first dielectric layer 414 , a bottom electrode 108, a resistive layer 110, and a top electrode 106; wherein the semiconductor substrate comprises a plurality of vias 404b filled with a metal material; the first dielectric layer 414 is arranged on the semiconductor substrate, a plurality of
Regarding Claim 4, an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110 and an upper surface of the top electrode 106 in the trench.
Regarding Claim 5, in Figs.18-20, Lin et al. discloses a method for manufacturing a semiconductor device, comprising: depositing a first dielectric layer material 414 on a semiconductor substrate, and etching the first dielectric layer material to form a trench (1802, Fig. 18) corresponding to each via 404b in the semiconductor substrate in a first dielectric layer, the via being filled with a metal material; depositing a bottom electrode material 108 in the trench, and etching the bottom electrode material to form a bottom electrode covering a bottom of the trench; depositing a resistive layer material 110 to form a resistive layer covering an upper surface of the bottom electrode and a sidewall of the trench; depositing a second dielectric layer material 112/104 or a thermally enhanced layer material 112/104 in a groove of the resistive layer (please note that resistive layer is U-shaped and hence the inherent presence of groove), and etching the second dielectric layer material or the thermally enhanced layer material to form a second dielectric layer or a thermally enhanced layer 110/104 covering a sidewall of the groove; and filling a top electrode material 106 in a cavity (again the layers are U-shaped and hence the inherent presence of cavity) formed by the second dielectric layer or the thermally enhanced layer and the resistive layer to form a top electrode 106.
Regarding Claim 6, performing planarization, wherein upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the second dielectric layer or the thermally enhanced layer in the trench 112/104.
Regarding Claim 7, semiconductor device manufactured by the method according to claim 5,comprising: a semiconductor substrate, a first dielectric layer 414, a bottom electrode 108, a resistive layer 110, and a top electrode 106; and further comprising a second dielectric layer or a thermally enhanced layer 112/104; wherein the semiconductor substrate comprises a plurality of vias 404b filled with a metal material; the first dielectric layer is arranged on the semiconductor substrate, a plurality of trenches (1802, see Fig. 18) are formed in the first dielectric layer, and the plurality of trenches are in a one-to-one correspondence with the plurality of vias; the bottom electrode 108 covers a bottom of the trench, and a lower surface of the bottom electrode contacts an upper surface of a corresponding via 404b; the resistive layer 110 covers an upper surface of the bottom electrode and a sidewall of the trench; the second dielectric layer or the thermally enhanced layer 112/104 covers a sidewall of a groove of the resistive layer, and a cavity is formed; and the top electrode is arranged in the cavity and fills the cavity (again, there is an inherent presence of cavity since the layers are in U shaped configuration).
Regarding Claim 8, an upper surface of the first dielectric layer 412 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the second dielectric layer or the thermally enhanced layer in the trench 112/104.
Regarding Claim 9, in Figs. 18-20, Lin et al. discloses a method for manufacturing a semiconductor device, comprising: depositing a first dielectric layer material 414 on a semiconductor substrate, and etching the first dielectric layer material to form a trench (1802, see Fig. 18) corresponding to each via 404b in the semiconductor substrate in a first dielectric layer, the via being filled with a metal material; depositing a bottom electrode material 108 in the trench, and etching the bottom electrode material to form a bottom electrode covering a bottom of the trench; depositing a resistive layer material 110 to form a resistive layer covering an upper surface of the bottom electrode and a sidewall of the trench; depositing a top electrode material 106 in a groove of the resistive layer to form a top electrode covering a bottom and a sidewall of the groove of the resistive layer; and filling a second dielectric layer material in a groove of the top electrode to form a second dielectric layer 112/104
Regarding Claim 10, performing planarization, wherein an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the second dielectric layer 112/104 in the trench.
Regarding Claim 11, a semiconductor device manufactured by the method according to claim 9,comprising: a semiconductor substrate, a first dielectric layer 414, a bottom electrode 106, a resistive layer 110, a top electrode 106, and a second dielectric layer 112/104 ; wherein the semiconductor substrate comprises a plurality of multiple vias 404b filled with a metal material; the first dielectric layer 414 is arranged on the semiconductor substrate ,a plurality of trenches 1802 (see Fig. 18) are formed in the first dielectric layer, and the plurality of trenches are in a one-to-one correspondence with the plurality of vias; the bottom electrode 108 covers a bottom of the trench, and a lower surface of the bottom electrode contacts an upper surface of a corresponding via; the resistive layer 110 covers an upper surface of the bottom electrode and a sidewall of the trench; the top electrode covers a bottom and a sidewall of a groove of the resistive layer; and the second dielectric layer 112/104 is filled in a groove of the top electrode.
Regarding Claim 12, an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the second dielectric layer 112/104 in the trench.
Regarding Claim 13, in Figs. 18-20, Lin et al. discloses a method for manufacturing a semiconductor device, comprising: depositing a first dielectric layer 414 material on a semiconductor substrate, and etching the first dielectric layer material to form a trench corresponding to each via in the semiconductor substrate in a first dielectric layer, the via being filled with a metal material; depositing a bottom electrode material 108 in the trench, and etching the bottom electrode material to form a bottom electrode covering a bottom of the trench; depositing a resistive layer material 108 to form a resistive layer 110 covering an upper surface of the bottom electrode and a sidewall of the trench; depositing a top electrode material 106 in a groove of the resistive layer, and etching the top electrode material to form a top electrode covering a sidewall of the groove of the resistive layer; and filling a second dielectric layer material 112/104 in a cavity formed by the top electrode and the resistive layer to form a second dielectric layer (please note the layers are in U-shaped configuration)
Regarding Claim 14, further comprising: performing planarization, wherein an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the second dielectric layer 112/104 in the trench (trench being 1802 in Fig. 18).
Regarding Claim 15, semiconductor device manufactured by the method according to claim 13,comprising: a semiconductor substrate, a first dielectric layer 414, a bottom electrode 108, a resistive layer 110, a top electrode 106, and a second dielectric layer 112/104; wherein the semiconductor substrate comprises a plurality of vias 404b filled with a metal material; the first dielectric layer is arranged on the semiconductor substrate, a plurality of trenches 1802 (Fig. 18) are formed in the first dielectric layer, and the plurality of trenches are in a one-to-one correspondence with the plurality of vias; the bottom electrode 108 covers a bottom of the trench, and a lower surface of the bottom electrode contacts an upper surface of a corresponding via; the resistive layer 110 covers an upper surface of the bottom electrode and a sidewall of the trench; the top electrode covers a sidewall of a groove of the resistive layer; and the second dielectric layer 112/104 is filled in a cavity formed by the top electrode and the resistive layer.
Regarding Claim 16, an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 1110, an upper surface of the top electrode 106, and an upper surface of the second dielectric layer 112/104 in the trench (trench being element 1802 in Fig. 18 and please note that these layers are in U-shaped configuration)
Regarding Claim 17, in Figs. 18-20, Lin et al. discloses a method for manufacturing a semiconductor device, comprising: depositing a first dielectric layer material 414 on a semiconductor substrate, and etching the first dielectric layer material to form a trench (1802, Fig. 18) corresponding to each via 404b in the semiconductor substrate in a first dielectric layer, the via being filled with a metal material; depositing a bottom electrode 108 material in the trench, and etching the bottom electrode material to form a bottom electrode covering a bottom of the trench; depositing a resistive layer material 110 to form a resistive layer covering an upper surface of the bottom electrode and a sidewall of the trench; depositing a thermally enhanced layer material 112/104 in a groove of the resistive layer to form a thermally enhanced layer covering a bottom and a sidewall of the groove of the resistive layer; and filling a top electrode material 106 in a groove of the thermally enhanced layer to form a top electrode.
Regarding Claim 18, performing planarization, wherein an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the thermally enhanced layer 112/104 in the trench (please note the U-shaped layer stack structure)
Regarding Claim 19, semiconductor device manufactured by the method according to claim 17,comprising: a semiconductor substrate, a first dielectric layer 414, a bottom electrode 108, a resistive layer 110, a top electrode 106, and a thermally enhanced layer 112/104; wherein the semiconductor substrate comprises a plurality of vias 404b filled with a metal material; the first dielectric layer is arranged on the semiconductor substrate, a plurality of
Regarding Claim 20, an upper surface of the first dielectric layer 414 is flush with an upper surface of the resistive layer 110, an upper surface of the top electrode 106, and an upper surface of the thermally enhanced layer 112/104 in the trench.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAZLI ERDEM/Primary Examiner, Art Unit 2812 7/18/2026
Prosecution Insights