DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed on 11/26/2025, with respect to the claim rejections have been fully considered and are persuasive. The Office Action of 10/02/2025 has been withdrawn.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10 recites in line 4 “word lines (2), wherein values that represent a first set of input values (1) can be applied to the word lines (2) the input values (1) being defined by phase or amplitude.” It seems the limitation has incomplete sentence. A possible correction “…,wherein the first set of the input values being defined by a phase or amplitude.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the input values" in e.g. line 5. There is insufficient antecedent basis for this limitation in the claim. A possible correction “the first set of input values.”
Claims 16 and 18 recite “wherein the matrix consists exclusively of capacitive elements” However, claim 10 recites the matrix comprises resistive elements and capacitive elements. It is impossible to have a matrix comprising resistive elements and capacitive elements and at the same time the matrix consists exclusively of capacitive elements. Therefore, the claims are indefinite.
Claims 17 and 19 recite “wherein the matrix consists exclusively of resistive elements” However, claim 10 recites the matrix comprises resistive elements and capacitive elements. It is impossible to have a matrix comprising resistive elements and capacitive elements and at the same time the matrix consists exclusively of resistive elements. Therefore, the claims are indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10, 12, 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strachan et al. (US 2018/0373675 A1), and further in view of Hatcher et al. (US 2019/0080230 A1).
Regarding claim 10, Strachan teaches a matrix assembly, comprising:
a matrix of resistive devices (5), wherein resistance values of the resistive devices (5) represent coefficients of a discrete Fourier matrix (Fig. 2, matrix device 126, ¶0020);
word lines (2), wherein values that represent a first set of input values (1) can be applied to the word lines (2) the input values (1) being defined by phase or amplitude (Fig. 2, word lines 204, ¶0011);
bit lines ( 4), wherein values that represent a second set of output values (3) can be applied to the bit lines ( 4) (Fig. 2, bit lines 206);
a current amplifier that is able to be connected to the bit lines (4) and sums the output values (3) (Fig. 2, current amplifier 124); and
Strachan is silent in teaching capacitive elements (6) that are designed to be able to store a capacitive value.
Hatcher teaches capacitive elements (6) that are designed to be able to store a capacitive value (Fig. 5A).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to use Hatcher’s hardware implementations in order to have a faster and more power efficient multiply and accumulate (MAC) circuitry.
Regarding claim 12, Strachan further teaches the matrix assembly as claimed in claim 10, wherein the input values are additionally defined by a number of periods (1) (¶0019).
Regarding claim 13, Strachan further teaches the matrix assembly as claimed in claim 10, wherein the current amplifier is a phase-sensitive amplifier (¶0009).
Regarding claim 15, Hatcher further teaches the matrix assembly as claimed in claim 10, wherein the resistance value of the resistive devices (5) represents a real part of the coefficients of the matrix and the capacitance value of the capacitive elements (6) represents an imaginary part of the coefficients of the matrix (¶0021).
Currently claims 16-19 are only rejected under 35 U.S.C. 112(b) above. No art rejection applied.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strachan and Hatcher as applied to claim 10 above, and further in view of Bratkovski et al (US 2012/0039114 A1).
Regarding claim 11, Strachan and Hatcher are silent in teaching wherein the capacitive elements (6) are memcapacitive elements.
Bratkovski teaches the capacitive elements (6) are memcapacitive elements (Fig. 1A).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to use memcapacitive elements for their advantages by having a relatively simple construction, small footprint, retention of its state without the application of electrical power, and does not bleed energy during operation.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strachan and Hatcher as applied to claim 13 above, and further in view of Baker (US 6,885,580 B2).
Regarding claim 14, Strachan further teaches the matrix assembly as claimed in claim 13, wherein the phase-sensitive amplifier (8) contains two inputs (Fig. 2, sense amplifiers 124 contains two inputs)
Strachan is silent in teaching two input-side switches (9) that switch in opposition, and wherein a switching state is determined by a clock signal (10), and wherein clock signals for a real part have a 0° phase shift and clock signals for an imaginary part have a 90° phase shift, wherein half-cycles of the output signal are always connected to noninverting (11) and inverting (12) inputs of the phase-sensitive amplifier (8).
Baker teaches two input-side switches (9) that switch in opposition, and wherein a switching state is determined by a clock signal (10), and wherein clock signals for a real part have a 0° phase shift and clock signals for an imaginary part have a 90° phase shift, wherein half-cycles of the output signal are always connected to noninverting (11) and inverting (12) inputs of the phase-sensitive amplifier (8) (Fig. 8, teaches two input-side switches 920. Where the output signal UP are always connected to the noninverting and inverting (919) inputs of the sense amplifier 917).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to use Baker’s switching circuitry with the sense amplifier in order to reduce the power dissipation within the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
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