CTNF 18/687,589 CTNF 87160 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes: PHOTODETECTION DEVICE WITH PARALLEL MULTIPLIERS IN EACH PIXEL Drawings 06-22 AIA The drawings are objected to because in FIGS. 2, 7, 9, and 11, there are lines from reference numbers for which it is not entirely clear where the lines end, that is, what the reference numbers correspond to; particularly 24 in FIGS. 2, 9, and 11; and 25, 24, and 15 in FIG. 7 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites that “each of the pixels further includes a metal wiring line that electrically couples respective portions of the plurality of multipliers on the quench section side to each other.” It is not entirely clear what this means. For present purposes, the metal wiring line coupled to the multipliers is on the same side of the multipliers as the quench section is. Claim 6 recites that “in each of the pixels, the plurality of multipliers is disposed at positions closer to a middle in a pixel region opposed to the photoelectric converter in a plan view.” This has two problems. First, claim 6 does not recite what the multipliers are closer to the middle than, so the scope of the claim can not be determined. Secondly, it is not clear what “in a pixel region opposed to the photoelectric converter in a plan view” means. The remaining claims are rejected based on their dependencies. 07-30-03-h AIA Claim Interpretation Claim 1 recites “a quench section coupled to the plurality of multipliers on a side opposite to a coupling side to the photoelectric converter.” The examiner understands the “coupling side” to refer to the side on which the multipliers are coupled to the photoelectric converter. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 14, and 15 are rejected under 35 USC 102( a)(1) as being anticipated by Miura, WO 2021/124697 A1, and under 35 U.S.C. 102(a)(2 ) as being anticipated by the corresponding US publication of Miura, US 2023/0011366 A1. As these are corresponding references, citations here will only be to the US publication . Claim 1: Miura discloses a photodetection device ([0064]) comprising a plurality of pixels (3) arranged two-dimensionally (FIG. 1), each of the pixels including: a photoelectric converter (14); a plurality of multipliers (18) coupled in parallel to each other and coupled in series to the photoelectric converter; and a quench section (7) coupled to the plurality of multipliers on a side opposite to a coupling side to the photoelectric converter (FIG. 5B). PNG media_image1.png 448 496 media_image1.png Greyscale Claim 14: An imaging device ([0054]) comprising a plurality of pixels (3) arranged two-dimensionally (FIG. 1), each of the pixels including: a photoelectric converter (14); a plurality of multipliers (18) coupled in parallel to each other and coupled in series to the photoelectric converter; and a quench section (7) coupled to the plurality of multipliers on a side opposite to a coupling side to the photoelectric converter (FIG. 5B). Claim 15: Miura discloses distance measurement apparatus comprising a photodetection device ([0054]), the photodetection device including a plurality of pixels (3) arranged two-dimensionally (FIG. 1), each of the pixels including: a photoelectric converter (14); a plurality of multipliers (18) coupled in parallel to each other and coupled in series to the photoelectric converter; and a quench section (7) coupled to the plurality of multipliers on a side opposite to a coupling side to the photoelectric converter (FIG. 5B) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-9, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto, US 2018/0108800 A1, in view of Miura . Claim 1: Morimoto discloses a photodetection device ([0055]) comprising a plurality of pixels (100) arranged two-dimensionally (FIG. 4), each of the pixels including: a photoelectric converter (5); a plurality of multipliers (1+4) coupled in parallel to each other and coupled in series to the photoelectric converter; and a quench section (202). Morimoto discloses in FIG. 16 that the quench section 202 is coupled to the multiplier 1+4 on a side opposite to a coupling side to the photoelectric converter. Morimoto does not disclose how the embodiment of FIG. 14 connects the multipliers and the quench sections. However, Miura FIG. 5B shows two multipliers 18 that are connected in parallel to a single quench section 7. Therefore it would have been obvious to have connected the two multipliers of Morimoto to a single quench section as known in the art as an effective arrangement for forming photoelectric conversion, with the advantage of reducing resistance (Miura [0099]). Claim 2: each of the pixels further includes a metal wiring line (18/9) that electrically couples respective portions of the plurality of multipliers on the quench section side to each other. In Morimoto in view of Miura, it would have been obvious to have connected the lines together in order to feed into a single quench section 202. Claim 3: Morimoto discloses a semiconductor substrate (Morimoto, bottom portion of 15, FIG. 16) and an interlayer insulating film (top portion of 15) that is formed in contact with the semiconductor substrate, wherein in each of the pixels, the photoelectric converter includes a semiconductor region (5) of a predetermined electrical conduction type (N, [0080]) that is formed in a single region at a predetermined depth in the semiconductor substrate, the plurality of multipliers is formed in a pn junction region (junction of p region 4 and n region 1) that is formed in a region of the semiconductor substrate, the region being shallower than the photoelectric converter and being closer to the wiring layer, and the metal wiring line is formed in the interlayer insulating film and in contact with the plurality of multipliers (FIG. 16). PNG media_image2.png 456 614 media_image2.png Greyscale Claim 4: Morimoto discloses a signal processing substrate (1102) bonded to the semiconductor substrate with the interlayer insulating film interposed between the semiconductor substrate and the signal processing substrate, wherein the signal processing substrate includes a signal processor electrically coupled to the metal wiring line (FIG. 16), and the signal processor processes an output from the plurality of multipliers. “To increase the aperture ratio of the photoelectric conversion element 101, the pixel signal processing unit 102 may be provided on a different semiconductor substrate from that of the photoelectric conversion element 101. In such a case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are electrically connected by connection wiring provided for each pixel.” [0062]. Claim 5: the interlayer insulating film and the signal processing substrate are electrically coupled to each other by joining copper pads (1105) provided on respective joint surfaces of the interlayer insulating film and the signal processing substrate to each other (FIG. 16). Claim 6: Morimoto does not specifically discloses that in each of the pixels, the plurality of multipliers is disposed at positions closer to a middle in a pixel region opposed to the photoelectric converter in a plan view. However, the precise positions of the multipliers would be a matter of design choice, and this would not be a source of patentable distinction absent unexpected results. Claim 7, in each of the pixels, the plurality of multipliers is disposed at positions in the pixel region excluding a center of the pixel region (FIGS 15A and 15B). PNG media_image3.png 322 514 media_image3.png Greyscale Claim 8: of the pixels further includes, in a same layer as the plurality of multipliers in the semiconductor substrate, a separation section (16) that separates the plurality of multipliers from each other. Claim 9: the separation section includes an ion implant (P-type, [0083]-[0084]) formed in the semiconductor substrate. Claim 14: Morimoto discloses an imaging device ([0074]) comprising a plurality of pixels (100) arranged two-dimensionally (FIG. 4), each of the pixels including: a photoelectric converter (5); a plurality of multipliers (1+4) coupled in parallel to each other and coupled in series to the photoelectric converter; and a quench section (202). Morimoto discloses in FIG. 16 that the quench section 202 is coupled to the multiplier 1+4 on a side opposite to a coupling side to the photoelectric converter. Morimoto does not disclose how the embodiment of FIG. 14 connects the multipliers and the quench sections. However, Miura FIG. 5B shows two multipliers 18 that are connected in parallel to a single quench section 7. Therefore it would have been obvious to have connected the two multipliers of Morimoto to a single quench section as known in the art as an effective arrangement for forming photoelectric conversion, with the advantage of reducing resistance (Miura [0099]). Claim 15: Morimoto discloses a distance measurement apparatus ([0203]) comprising a photodetection device ([0204]), the photodetection device including a plurality of pixels (100) arranged two-dimensionally (FIG. 4), each of the pixels including: a photoelectric converter (5); a plurality of multipliers (1+4) coupled in parallel to each other and coupled in series to the photoelectric converter; and a quench section (202). Morimoto discloses in FIG. 16 that the quench section 202 is coupled to the multiplier 1+4 on a side opposite to a coupling side to the photoelectric converter. Morimoto does not disclose how the embodiment of FIG. 14 connects the multipliers and the quench sections. However, Miura FIG. 5B shows two multipliers 18 that are connected in parallel to a single quench section 7. Therefore it would have been obvious to have connected the two multipliers of Morimoto to a single quench section as known in the art as an effective arrangement for forming photoelectric conversion, with the advantage of reducing resistance (Miura [0099]) . 07-21-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Morimoto in view of Miura and Inui, US 2020/0273894. Morimoto does not disclose that the separation section includes an STI (a shallow trench isolation) formed in the semiconductor substrate. However, this was a common arrangement. See Inui: “Each of the isolation portions 16A and 16B may be an insulating isolation region formed by local oxidation of silicon (LOCOS), shallow trench isolation (STI), deep trench isolation (DTI), or the like.” [0051] . 07-21-aia AIA Claim s 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto in view of Miura and Kobayashi, US 2019/0181177 A1 . Claim 11: Morimoto discloses a semiconductor substrate (bottom of 15, FIG. 16) in which the photoelectric converter and the plurality of multipliers (4+1) are formed, wherein each of the multipliers is formed in a region, of the semiconductor substrate, in which a first semiconductor region (4) of a first electrical conduction type (P) and a second semiconductor region (1) of a second electrical conduction type (N) join to each other. Morimoto does not disclose that the semiconductor substrate further includes, in each of the pixels, a third semiconductor region of the first electrical conduction type that is in contact with each of a plurality of the first semiconductor regions. Kobayashi discloses a third semiconductor region (32a) of the first electrical conduction type (the same type as the first semiconductor region 32, [0118]-[0119]) that is in contact with each of a plurality of the first semiconductor regions (32). It would have been obvious to have had such a higher-doped portion in order to facilitate connection to the wiring ([0119]). Claim 12: a concentration of an impurity of the first electrical conduction type in the third semiconductor region is higher than a concentration of the impurity of the first electrical conduction type in the first semiconductor region (Kobayashi [0118]-[0119]) . 07-21-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Morimoto in view of Miura, Kobayashi, and Leem, US 2009/0116523 A1. Kobayashi does not explicitly disclose the claimed fourth semiconductor region. However, it was well-know that implantation would often not result in an even distribution of ions. Leem discloses that “as is well-known, due to atomic collisions during an ion implantation process and a subsequent diffusion of atoms, spatial distribution of impurity concentration, which is implanted through ion implantation technique, is close to Gaussian distribution. That is, the impurity region 24 has a gradient of concentration. Accordingly, a boundary of the impurity region 24 may not be discretely defined in both a vertical direction and a horizontal direction.” [0011]. That is, the outer boundary of the implantation region has a lower concentration of ions than the central portion of the implantation region. Therefore, by forming doping region 32a by a well-known process (ion implantation), it would be likely that a lower-concentration outer (bottom and side) region that would be lower concentration. Thus the lower concentration outer region would correspond to the claimed third region, and the higher concentration central region would correspond to the claimed fourth region. Thus, in Miura in view of Kobayashi and Leem, each of the pixels would have a fourth semiconductor region of the first electrical conduction type that is smaller in number than the multipliers (there are two multipliers and one contact, and thus only one fourth region is necessary), the fourth semiconductor region being in contact with the third semiconductor region and serving as a contact section, and the concentration of the impurity of the first electrical conduction type in the third semiconductor region is lower than a concentration of the impurity of the first electrical conduction type in the fourth semiconductor region . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Morimoto, US 2018/0033896 A1, also disclosing two multipliers in one pixel (FIG. 11) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER BRADFORD/Primary Examiner, Art Unit 2897 Application/Control Number: 18/687,589 Page 2 Art Unit: 2897 Application/Control Number: 18/687,589 Page 3 Art Unit: 2897 Application/Control Number: 18/687,589 Page 4 Art Unit: 2897 Application/Control Number: 18/687,589 Page 5 Art Unit: 2897 Application/Control Number: 18/687,589 Page 6 Art Unit: 2897 Application/Control Number: 18/687,589 Page 7 Art Unit: 2897 Application/Control Number: 18/687,589 Page 9 Art Unit: 2897 Application/Control Number: 18/687,589 Page 10 Art Unit: 2897 Application/Control Number: 18/687,589 Page 11 Art Unit: 2897 Application/Control Number: 18/687,589 Page 12 Art Unit: 2897 Application/Control Number: 18/687,589 Page 13 Art Unit: 2897 Application/Control Number: 18/687,589 Page 14 Art Unit: 2897 Application/Control Number: 18/687,589 Page 15 Art Unit: 2897 Application/Control Number: 18/687,589 Page 16 Art Unit: 2897
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