DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2022/0216284 to Jeon et al (hereinafter Jeon).
Regarding Claim 1, Jeon discloses a display substrate, comprising
a display region (Fig. 1, 100), wherein the display region comprises
a drive circuit layer (Fig. 10) disposed on a base substrate and a light emitting structure layer (IL5) disposed at a side of the drive circuit layer away from the base substrate,
the drive circuit layer comprises
a plurality of circuit units (T1, Fig. 10),
a plurality of data signal lines (DL),
a plurality of data connection lines (300),
a plurality of low-voltage power supply lines (ELVSS), and
a plurality of power supply traces (113),
the light emitting structure layer comprises a plurality of light emitting devices (EL),
the circuit units comprise pixel drive circuits (Fig. 10),
the data signal lines are configured to provide data signals to the pixel drive circuits (Fig. 1),
the low-voltage power supply lines are configured to continuously provide low power supply voltage signals to the light emitting devices [0050];
the data connection lines are connected with the data signal lines, and the power supply traces are connected with the low-voltage power supply lines (Fig. 1).
Regarding Claim 27, Jeon discloses a display apparatus comprising a display substrate according to Claim 1 (Fig. 1)
Allowable Subject Matter
Claims 2-21, 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites the display substrate according to Claim 1, wherein
a data connection line comprises a first connection line extending along a first direction and a second connection line extending along a second direction, the first connection line is connected with the second connection line,
a power supply trace comprises a first power supply trace extending along the first direction and a second power supply trace extending along the second direction, the first power supply trace is connected with the second power supply trace, the first direction and the second direction intersect;
on a plane parallel to the base substrate, the display region comprises at least a first region provided with the first connection line, at least one circuit unit of the first region comprises the first connection line, the first power supply trace, and the second power supply trace, a data signal line and a low-voltage power supply line are in a shape of a line extending along the second direction,
the first connection line is connected with the data signal line, the second power supply trace is disposed between the low-voltage power supply line and the data signal line, and the second power supply trace is connected with the low-voltage power supply line.
Claim 24 recites the display substrate according to Claim 1, wherein the pixel drive circuit at least comprises a storage capacitor and a plurality of transistors;
on a plane perpendicular to the base substrate, the drive circuit layer comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed sequentially on the base substrate,
wherein the semiconductor layer at least comprises active layers of the plurality of transistors,
the first conductive layer at least comprises gate electrodes of the plurality of transistors and a first electrode plate of the storage capacitor,
the second conductive layer at least comprises a second electrode plate of the storage capacitor,
the third conductive layer at least comprises first electrodes and second electrodes of the plurality of transistors,
the fourth conductive layer at least comprises the data signal line and the low-voltage power supply line, and
the fifth conductive layer at least comprises the data connection line and the power supply trace.
While Jeon discloses the basic components of a display device as claimed by Applicant, Jeon does not disclose the circuit design or conductive layers claimed in Claims 2 or 24. US PG Pub 2022/0181428 (“Kobayashi”) and US PG Pub 2019/0206955 (“Paek”) are cited as being examples of other, relevant references in the art for comparison to Applicant’s invention. While the references disclose various embodiments for display device circuit layouts, they do not disclose, or suggest, the circuit design or conductive layers claimed by Applicant.
A search of other, relevant references does not show Applicant’s invention to be anticipated or obvious. Claims 3-21 and 25 depend on one of Claims 2 or 24 and are allowable for at least the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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