Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED OFFICE ACTION
Status of Claims
Claims 1-12,28-31 and 45-48 are pending examination.
Claims 13-27,32-44 and 49-94 are cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b) (2) (C) for any potential 35 U.S.C. 102(a) (2) prior art against the later invention.
1. Claims 1 and 2 are rejected under 35 U.S.C 103(a) as being unpatentable over Heroux et al. (USPUB 20180267236) in view of Pranay Koka et al. ( NPL DOC: "Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems," 19th June 2010, ACM SIGARCH Computer Architecture News, Volume 38, Issue 3,ISCA’10, June 19–23, 2010, Saint-Malo, France,Pages 117-123.).
As per claim 1, Heroux et al. teaches An apparatus comprising: an integrated circuit comprising a plurality of nodes coupled to an optical network ( FIG.1 and Paragraph [0027]- “…Using the waveguide architecture shown in FIG. 1, a photonic neural component 100 can support photonic spike computing by optical signal transmission with low loss via waveguides formed so as to cross one another on a board, e.g., a printed circuit board. The disclosed waveguide architecture can, therefore, allow for design flexibility (e.g., layout, materials, etc.) while lifting the speed restriction of the conventional electronic approach. The photonic neural component 100 includes a plurality of optical transmitter chips 110A to 110D, a plurality of optical receiver chips 120A to 120D,…”) , each node comprising: an optical transmitter interface configured to transmit an optical signal at a location along a coupled optical path of the optical network ( Paragraph [0027]- “… The photonic neural component 100 includes a plurality of optical transmitter chips 110A to 110D,…” AND Paragraphs [0033-0034] AND Paragraph [0038]- “… FIG. 1, each of the optical transmitter chips 110A to 110D includes the same number of optical transmitters (e.g., four optical transmitters 110A-1 to 110A-4 for optical transmitter chip 110A) and each of the optical receiver chips 120A to 120D includes the same number of optical receivers (e.g., four optical receivers 120A-1 to 120A-4 for optical receiver chip 120A). Moreover, the number of optical transmitters (e.g., four) included in each of the optical transmitter chips 110A to 110D is the same as the number of optical receivers (e.g., four) included in each of the optical receiver chips 120A to 120D….”) , and an optical receiver interface configured to receive an optical signal at a location along the coupled optical path of the optical network ( Paragraph [0037-0038]- “…each of the optical receiver chips 120A to 120D includes the same number of optical receivers (e.g., four optical receivers 120A-1 to 120A-4 for optical receiver chip 120A). Moreover, the number of optical transmitters (e.g., four) included in each of the optical transmitter chips 110A to 110D is the same as the number of optical receivers (e.g., four) included in each of the optical receiver chips 120A to 120D. …”) ;a first optical path of the optical network including at least a portion fabricated in at least one layer of the integrated circuit and configured to propagate a guided mode around a closed path ( FIG. 7 and FIG.8 teaching the connectivity path of the nodes within the semiconductor chip and further taught within Paragraph [0050]- “… the multiplexers 140A to 140D of the photonic neural component 100 may be manufactured by forming a lower clad layer in a layer of a board, forming a core layer on the lower clad layer, and forming an upper clad layer on the core layer. The lower and upper clad layers may be formed, for example, by applying a first polymer using spin coating or curtain coating and baking. The lower and upper clad layers may be shared by multiple parallel waveguides. …”) ; and a second optical path of the optical network including at least a portion fabricated in at least one layer of the integrated circuit and configured to propagate a guided mode around a closed path (Paragraph [0044]- “… FIG. 3. That is, the wavelengths λA, λB, λC, and λD are the wavelengths of the optical signals emitted by the optical transmitter chips 110A, 110B, 110C, and 110D, respectively. As further described by way of example with respect to FIG. 3, such optical signals of four wavelengths may propagate on each of the inter-node waveguides 130-1, 130-2, 130-3, and 130-4 and may be reflected by the mirror 160A such that reflected optical signals of each of the four wavelengths (or three out of four, depending on the configuration of the mirrors 160A to 160D) is transmitted by each receiving waveguide 170A-1, 170A-2, 170A-3, and 170A-4 to the optical receiver chip 120A….” AND optical signals propagating on each of the inter-node waveguides taught within Paragraphs [0034 ] and [0039]) ;
Heroux et al. does not explicitly teach wherein: the first and second optical paths overlap with each other at a first set of four locations on the integrated circuit, the first optical path is coupled to two or more of the plurality of nodes at a second set of respective locations on the integrated circuit different from all of the locations in the first set of locations, and the second optical path is coupled to two or more of the plurality of nodes at a third set of respective locations on the integrated circuit different from all of the locations in the first and second sets of locations.
However, within analogous art, Pranay Koka et al. teaches wherein: the first and second optical paths overlap with each other at a first set of four locations on the integrated circuit (Page 10-Figure 3 and Col. 2 – “…A smaller 125mm2 processor die sits face-down, partly overlapping the memory and the SOI substrate and spanning the two. The processor and memory die are connected using electrical proximity [12]. Additional memory can be located the macrochip and accessed via optical fibers. The processor is a multi-core die with memory controllers, a cache hierarchy, and an intra-die interconnect network [10]. The details of the processor die are beyond the scope of this paper. The processor and memory die connect using electrical proximity communication [12]. The processor die also includes optical transmitters, receivers, and waveguides positioned to overlap the SOI routing substrate, and uses OPxC to connect its waveguides to those in the SOI routing substrate …”),the first optical path is coupled to two or more of the plurality of nodes at a second set of respective locations on the integrated circuit different from all of the locations in the first set of locations ( Page 121- Col.1 – “…optical switches with multiple host access points to interconnect compute nodes. Each compute node sets up a series of optical switches, using an independent optical/electrical path-setup network, to connect the node to the destination. No explicit arbitration among senders is required for data transmission. Depending on the topology and complexity, these networks are either blocking or non-blocking. A non-blocking network implies that a circuit established between any pair of nodes 'A' and 'B' will not block a circuit between any other pair of nodes 'C' and 'D'. We adapt the architecture of the optical circuit-switch…” AND Figure 4 and 5 showing the optical path coupling within the nodes ) , and the second optical path is coupled to two or more of the plurality of nodes at a third set of respective locations on the integrated circuit different from all of the locations in the first and second sets of locations ( Figure 4 and 5 and Page 123- Col. 1- “…The electronic network is a low-bandwidth packet-switched network and is used to set up an optical path from the source to the destination. Each switching point in the electronic network is attached to the 4x4 optical switch that it controls. To establish an optical circuit, a source node initiates a path-setup packet on the electronic network from its gateway; this setup packet is routed through multiple switch points to the destination. At each switch point the router sets the corresponding optical switch and routes the packet towards the destination site….”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Pranay Koka et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. because the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. provides a method and system for implementation of optical signal communication and routing within multi-chip optical systems.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. for implementing a system and method for optical signal communication and routing within multi-chip optical systems.
As per claim 2, Combination of Heroux et al. and Pranay Koka et al. teach claim 1,
Within analogous art, Pranay Koka et al. teaches wherein the first optical path comprises at least first and second straight segments that are parallel to each other ( Page 122- Col. 1- “…To minimize the optical loss through the switches, each waveguide is implemented as two parallel waveguide segments. We refer to the pair of segments that form a logical waveguide as simply waveguides in this section….”) , with at least one of the plurality of nodes coupled at two or more locations in the second set along the first straight segment and at least one of the plurality of nodes coupled at two or more locations in the second set along the second straight segment ( Page 123- Figure 5 showing the plurality of nodes and there connectivity and locations of the nodes and connectivity and furthermore taught within Page 121- Col. 1- “…These architectures use a network of waveguides and optical switches with multiple host access points to interconnect compute nodes. Each compute node sets up a series of optical switches, using an independent optical/electrical path-setup network, to connect the node to the destination. No explicit arbitration among senders is required for data transmission…”).
2. Claims 3,4,5,6 and 7 are rejected under 35 U.S.C 103(a) as being unpatentable over Heroux et al. (USPUB 20180267236) in view of Pranay Koka et al. ( NPL DOC: "Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems," 19th June 2010, ACM SIGARCH Computer Architecture News, Volume 38, Issue 3,ISCA’10, June 19–23, 2010, Saint-Malo, France,Pages 117-123.) in further view of Zheng et al.(USPUB 20100266276).
As per claim 3, Combination of Heroux et al. and Pranay Koka et al. teach claim 2,
Within analogous art, Zheng et al. teaches wherein the first and second optical paths overlap with each other at the first set of four locations without switching optical signals between the first and second optical paths at any of the four locations in the first set ( FIG. 1B and Paragraph [0083-0084]- “…FIG. 1B presents a block diagram illustrating a top view of an embodiment of MCM 130 (which may include a computer system and/or a switch). This MCM includes an array of multiple semiconductor dies 114 and bridge chips 116. Proximity connectors on the side edges (and in some embodiments on the corners) of the semiconductor dies 114 and the bridge chips 116 overlap and couple signals between adjacent components in the MCM 130 using electromagnetic proximity communication,…”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Zheng et al. within the combined modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. and the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. because the Broadband and wavelength-selective bidirectional 3-way optical splitter mentioned by Zheng et al. provides a method and system for implementation of multi-chip system within semiconductor dies for optical communication.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. for implementing a system and method for optical signal communication and routing within multi-chip optical systems.
As per claim 4, Combination of Heroux et al. and Pranay Koka et al. and Zheng et al. teach claim 3,
Within analogous art, Zheng et al. teaches wherein, at least one of the four locations in the first set, a portion of the first optical path in a first layer of the integrated circuit overlaps with a portion of the second optical path in a second layer of the integrated circuit ( Paragraphs [0101-0102]- “…different connectors may be overlapped on adjacent semiconductor dies 210. For example, one embodiment of the present invention uses inductive proximity connectors and/or magnetic proximity connectors, where data signals are communicated inductively and/or magnetically between terminals on closely adjacent semiconductor dies 210. …”) .
As per claim 5, Combination of Heroux et al. and Pranay Koka et al. and Zheng et al. teach claim 4,
Within analogous art, Zheng et al. teaches wherein, at least one location on the integrated circuit, a portion of the second optical path is in the first layer of the integrated circuit ( Paragraph [0093]- “…one semiconductor die 210, where semiconductor die 210 may include integrated circuit electronics corresponding to layers deposited on a semiconductor substrate. Note that semiconductor die 210 may be packaged in an SCM and/or an MCM, where the MCM may include two or more SCMs….”) .
As per claim 6, Combination of Heroux et al. and Pranay Koka et al. and Zheng et al. teach claim 5 ,
Within analogous art, Zheng et al. teaches wherein at least one of the plurality of nodes is coupled to the first optical path at one or more locations in the second set of locations and is coupled to the second optical path at one or more locations in the third set of locations ( plurality of nodes shown within FIG. 1A-1B and FIG. 7 and FIG. 11 and FIG. 16 and the optical path /waveguide taught connecting the nodes furthermore taught within Paragraphs [0171-0172] and Paragraph [0200-0203]) .
As per claim 7, Combination of Heroux et al. and Pranay Koka et al. teach claim 2,
Within analogous art, Zheng et al. teaches wherein the first and second optical paths overlap with each other with at least one switch configured to switch optical signals between the first and second optical paths at least one of the four locations in the first set ( Paragraphs [0081-0082]- “…proximity connectors on the corners (and more generally on side edges) of the semiconductor dies 110 and 112 overlap and couple signals between adjacent semiconductor dies using electromagnetic proximity communication, such as capacitive and/or optical proximity communication… one or more of the semiconductor dies 110 and 112 implement some or all of the functionality of a switch. Such semiconductor dies are sometimes referred to as `switch chips` or `logic chips….”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Zheng et al. within the combined modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. and the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. because the Broadband and wavelength-selective bidirectional 3-way optical splitter mentioned by Zheng et al. provides a method and system for implementation of multi-chip system within semiconductor dies for optical communication.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. for implementing a system and method for optical signal communication and routing within multi-chip optical systems.
3. Claims 8 and 9 are rejected under 35 U.S.C 103(a) as being unpatentable over Heroux et al. (USPUB 20180267236) in view of Pranay Koka et al. ( NPL DOC: "Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems," 19th June 2010, ACM SIGARCH Computer Architecture News, Volume 38, Issue 3,ISCA’10, June 19–23, 2010, Saint-Malo, France,Pages 117-123.) in further view of Zheng et al.(USPUB 20100266276) and Wen et al. ( USPUB 20160337041).
As per claim 8, Combination of Heroux et al. and Pranay Koka et al. and Zheng et al. teach claim 7,
Within analogous art, Wen et al. teaches wherein the first and second optical paths are fabricated in the same layer of the integrated circuit ( Paragraph[0032]- “… the modulator 159 can be designed to be located at the middle of an optical path comprising both light path 156 and light path 158. Practical fabrication may have some tolerance. Assuming that the incoming optical carrier 141 has a rotation angle θ relative to the TE polarization of PBS 155…”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Wen et al within the combined modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. and the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. and the Broadband and wavelength-selective bidirectional 3-way optical splitter mentioned by Zheng et al. because the Polarization Independent Reflective Modulator mentioned by Wen et al. provides a method and system for implementation of optical carrier signal distribution within optical integrated system.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Polarization Independent Reflective Modulator mentioned by Wen et al. within the combined modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. and the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. and the Broadband and wavelength-selective bidirectional 3-way optical splitter mentioned by Zheng et al. for implementing a system and method for optical carrier signal distribution within optical integrated system.
As per claim 9, Combination of Heroux et al. and Pranay Koka et al. and Zheng et al. and wen et al. teach claim 8,
Within analogous art, Wen et al. teaches wherein the switch comprises at least two waveguide ring resonators in proximity to one of the four locations in the first set at which the first and second optical paths overlap with each other ( Paragraph [0029]- “…a micro-ring resonator based modulator, etc. Modulator 159 comprises a proximate end and a distal end coupled to light path 156 and light path 158, respectively. Modulator 159 is configured to receive the light beam in CCW direction at the proximate end and receive the light beam in clockwise direction at the distal end…”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Wen et al within the combined modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. and the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. and the Broadband and wavelength-selective bidirectional 3-way optical splitter mentioned by Zheng et al. because the Polarization Independent Reflective Modulator mentioned by Wen et al. provides a method and system for implementation of optical carrier signal distribution within optical integrated system.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Polarization Independent Reflective Modulator mentioned by Wen et al. within the combined modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. and the Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems mentioned by Pranay Koka et al. and the Broadband and wavelength-selective bidirectional 3-way optical splitter mentioned by Zheng et al. for implementing a system and method for optical carrier signal distribution within optical integrated system.
4. Claims 28,29 and 45 are rejected under 35 U.S.C 103(a) as being unpatentable over Heroux et al. (USPUB 20180267236) in view of Assaf Shacham et al. ( NPL DOC: " Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors," 28th April 2008,IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 9, SEPTEMBER 2008,Pages 1246-1255.).
As per claim 28, Heroux et al. teaches An apparatus comprising: an array of nodes ( Paragraph
[0034]-“… a printed circuit board, each mirror 160A to 160D arranged to partially reflect an optical signal propagating on an inter-node waveguide of the plurality of inter-node waveguides 130-1 to 130-4 to produce a reflected optical signal. For example, the mirror 160A may partially reflect optical signals propagating on each of the inter-node waveguides 130-1 to 130-4. Similarly, each of the mirrors 160B to 160D may partially reflect optical signals propagating on each of the inter-node waveguides 130-1 to 130-4. As used throughout this disclosure, the term “mirror” may refer to a plurality of mirror elements arranged as a mirror array. For example, the mirror 160A may include a plurality of mirror elements that separately reflect the optical signals propagating on each of the inter-node waveguides 130-1, 130-2, 130-3, and 130-4 or a plurality thereof. Also, the term “mirror” may refer to a single mirror element of such a mirror array. …”) ; an optical network comprising a first optical path and a second optical path (Paragraphs [0031-0032]-“…The plurality of inter-node waveguides 130-1 to 130-4 are formed on a board, e.g., a printed circuit board, and may be made of polymer in a single layer of the board. (Note that “on” a board is not limited to formation in an upper layer of the board and includes formation inside the board.) The plurality of inter-node waveguides 130-1 to 130-4 may be formed on the same board on which the optical transmitter chips 110A to 110D and/or optical receiver chips 120A to 120D are mounted. The plurality of inter-node waveguides 130-1 to 130-4 may be arranged as concentric loops, e.g., circles, ovals, ellipses, rounded squares or rectangles, rounded pentagons, or any other rounded polygons or other shapes that can be arranged as concentric loops. In a case where the plurality of optical transmitters 110A-1 to 110D-4 includes a first optical transmitter 110A-1 that emits an optical signal at a first wavelength and a second optical transmitter 110B-1 that emits an optical signal at a second wavelength different from the first wavelength, the inter-node waveguides 130-1 to 130-4 may include an inter-node waveguide that propagates the optical signal at the first wavelength and the optical signal at the second wavelength….”), in which the first optical path is configured to propagate a guided mode around a first closed path, the first optical path is optically coupled to a plurality of the nodes in the array( Paragraphs [0055-0056]-“… he optical transmitters and optical receivers (and equally the optical transmitter chips and optical receiver chips) can be divided into inner and outer groups associated with each ring. In the same way, the plurality of multiplexers 140A to 140H may include a first multiplexer group (e.g., multiplexers 140A to 140D), each multiplexer of the first multiplexer group configured to multiplex an input optical signal onto an inter-node waveguide of the first ring (e.g., inter-node waveguides 130-1 to 130-4), and a second multiplexer group (e.g., multiplexers 140E to 140H), each multiplexer of the second multiplexer group configured to multiplex an input optical signal onto an inter-node waveguide of the second ring (e.g., inter-node waveguides 130-5 to 130-8). Likewise, the plurality of mirrors 160A to 160H may include a first mirror group (e.g., mirrors 160A to 160D), each mirror of the first mirror group configured to partially reflect an optical signal propagating on an inter-node waveguide of the first ring (e.g., inter-node waveguides 130-1 to 130-4) to produce a reflected optical signal, and a second mirror group (e.g., mirrors 160E to 160H), each mirror of the second mirror group configured to partially reflect an optical signal propagating on an inter-node waveguide of the second ring (e.g., inter-node waveguides 130-5 to 130-8) to produce a reflected optical signal….”), the second optical path is configured to propagate a guided mode around a second closed path, the second optical path optically coupled to a plurality of the nodes in the array (Paragraph [0060]-“ … configured to emit an optical signal to be transmitted by the first input waveguide. Similarly, each of the optical transmitters of the second outer optical transmitter group (e.g., optical transmitters 110G-5 to 110G-8) may be optically connected to a second input waveguide of the plurality of second input waveguides (e.g., second input waveguides 730G-5 to 730G-8) and configured to emit an optical signal to be transmitted by the first input waveguide. That is, each second input waveguide (e.g., second input waveguide 730G-5, 730G-6, 730G-7, or 730G-8) may be optically connected to an optical transmitter of the second outer optical transmitter group (e.g., optical transmitter 110G-5, 110G-6, 110G-7, or 110G-8) and configured to receive an optical signal emitted from the optical transmitter and transmit the received optical signal to an inter-node waveguide of the second ring (e.g., inter-node waveguide 130-5, 130-6, 130-7, or 130-8) via a multiplexer of the second multiplexer group (e.g., multiplexer 140G)….”) ,
Heroux et al. does not explicitly teach the optical network is configured such that no switch is provided between the first and second optical paths such that an optical signal traveling in the first optical path remains in the first optical path and is not switched to the second optical path, and an optical signal traveling in the second optical path remains in the second optical path and is not switched to the first optical path; and a controller configured to schedule transmission of optical signals among the nodes through the optical network. However, within analogous art, Assaf Shacham et al. teaches the optical network is configured such that no switch is provided between the first and second optical paths such that an optical signal traveling in the first optical path remains in the first optical path and is not switched to the second optical path ( Page 4- Figure 2 showing the switch change ( ON-OFF) for routing optical signal with the optical path and further taught within Page -Col. 2- “…The switch is, in essence, a waveguide intersection, positioned between two ring resonators (Fig. 2). The rings have a certain resonance frequency, derived from material and structural properties.In the OFF state, when the resonant frequency of the rings is different from the wavelength (or wavelengths) on which the optical data stream is modulated, the light passes through the waveguide intersection uninterrupted, as if it isa passive waveguide crossover (Fig. 2a). When the switch is turned ON, by the injection of electrical current into p-n contacts surrounding the rings, the resonance of the rings shifts such that the transmitted light, now in resonance, is coupled into the rings making a right angle turn (Fig. 2b),thus creating a switching action….”) , and an optical signal traveling in the second optical path remains in the second optical path and is not switched to the first optical path ( Page 9- Figure 7 and Col. 1- “…Injection switch: messages already traveling on the torus network do not turn to the injection paths, so no blocking interactions exist between them and the injected messages.• Ejection Switch: messages may arrive only from the torus network and they either turn for ejection or continue straight through. Since no messages arrive from the gateway switch, none of the blocking interactions may happen. In Fig. 7 the three switches are shown with all the possible paths marked on them….” ) ; and a controller configured to schedule transmission of optical signals among the nodes through the optical network (controller set up for controlling the scheduling/timing of transmission signals taught within Page 9- Col. 1- “... When a path setup packet is sent, the gateway sets a timer to a predefined time. When the timer expires, a terminate-on time out packet is sent following the path-setup packet. The timeout packet follows the path acquired by the path-setup packet until it reaches the router where it is blocked. At that router, the path-setup packet is removed from the queue and a path-blocked packet is sent on the reverse path…” AND Page 11- Col.-2-“… a network on-chip combining a photonic circuit-switched network for high-bandwidth bulk data transmission and an electronic network which controls the photonic network while providing a medium for the exchange of short messages. The presentation covered critical design issues such as topology, routing algorithms, path-setup/teardown procedures, and deadlock avoidance rules and recovery procedures….”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Assaf Shacham et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. because the Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors mentioned by Assaf Shacham et al. provides a method and system for implementation of photonic circuit switching and control network within photonic networks on chip architecture.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors mentioned by Assaf Shacham et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. for implementing a system and method for photonic circuit switching and control network within photonic networks on chip architecture.
As per claim 29, Combination of Heroux et al. and Assaf Shacham et al. teaches claim 28,
Heroux et al. teaches wherein the first optical path is optically coupled to all of the nodes in the array, and the second optical path is optically coupled to all of the nodes in the array (Paragraph [0034]- “…each of the mirrors 160B to 160D may partially reflect optical signals propagating on each of the inter-node waveguides 130-1 to 130-4. As used throughout this disclosure, the term “mirror” may refer to a plurality of mirror elements arranged as a mirror array. For example, the mirror 160A may include a plurality of mirror elements that separately reflect the optical signals propagating on each of the inter-node waveguides 130-1, 130-2, 130-3, and 130-4 or a plurality thereof. Also, the term “mirror” may refer to a single mirror element of such a mirror array. …”) .
As per claim 45, Heroux et al. teaches An apparatus comprising: an array of nodes( Paragraph [0034]-“… a printed circuit board, each mirror 160A to 160D arranged to partially reflect an optical signal propagating on an inter-node waveguide of the plurality of inter-node waveguides 130-1 to 130-4 to produce a reflected optical signal. For example, the mirror 160A may partially reflect optical signals propagating on each of the inter-node waveguides 130-1 to 130-4. Similarly, each of the mirrors 160B to 160D may partially reflect optical signals propagating on each of the inter-node waveguides 130-1 to 130-4. As used throughout this disclosure, the term “mirror” may refer to a plurality of mirror elements arranged as a mirror array. For example, the mirror 160A may include a plurality of mirror elements that separately reflect the optical signals propagating on each of the inter-node waveguides 130-1, 130-2, 130-3, and 130-4 or a plurality thereof. Also, the term “mirror” may refer to a single mirror element of such a mirror array. …”); an optical network comprising a first optical loop and a second optical loop ( Paragraph [0053]- “… FIG. 1, the plurality of inter-node waveguides 130-1 to 130-4 includes a first ring (e.g., inter-node waveguides 130-1 to 130-4) having two or more of the inter-node waveguides arranged as concentric loops, the plurality of optical transmitters 110A-1 to 110D-4 includes a first inner optical transmitter group (e.g., optical transmitters 110A-1 to 110D-4) having two or more of the optical transmitters disposed inside the first ring, and the plurality of optical receivers 120A-1 to 120D-4 includes a first inner optical receiver group (e.g., optical receivers 120A-1 to 120D-4) having two or more of the optical receivers disposed inside the first ring. In the example of FIG. 7, similarly to FIG. 1, the plurality of inter-node waveguides 130-1 to 130-8 includes a first ring (e.g., inter-node waveguides 130-1 to 130-4) having two or more of the inter-node waveguides arranged as concentric loops, …”), in which the first optical loop is optically coupled to all of the nodes in the array ( FIG. 7 and 8 showing the optical interaction with all the nodes coupled optically) , the second optical loop is optically coupled to all of the nodes in the array ( Paragraph [0054]- “… the plurality of inter-node waveguides 130-1 to 130-8 may further include a second ring (e.g., inter-node waveguides 130-5 to 130-8) having two or more of the inter-node waveguides arranged as concentric loops, the plurality of optical transmitters 110A-1 to 110A-4, 110B-1 to 110B-4, 110C-1 to 110C-4, 110D-1 to 110D-4, 110E-5 to 110E-8, 110E-5 to 110E-8, 110G-5 to 110G-8, and 110H-5 to 110H-8 includes a second inner optical transmitter group (e.g., 110E-5 to 110E-8, 110E-5 to 110E-8, and 110H-5, to 110H-8) having two or more of the optical transmitters disposed inside the second ring, and the plurality of optical receivers 120A-1 to 120A-4, 120B-1 to 120B-4, 120C-1 to 120C-4, 120D-1 to 120D-4, 120E-5 to 120E-8, 120E-5 to 120E-8, 120G-5 to 120G-8, and 120H-5 to 120H-8 includes a second inner optical receiver group (e.g., 120E-5 to 120E-8, 120E-5 to 120E-8, and 120H-5, to 120H-8) having two or more of the optical receivers disposed inside the second ring….”) ;
Heroux et al. does not explicitly teach a controller configured to schedule transmission of optical signals among the nodes through the optical network, in which the controller is configured to permit only one node to broadcast an optical signal through the first optical loop during a first time period, prevent the other nodes from transmitting optical signals on the first optical loop during the first time period, permit only one node to broadcast an optical signal through the second optical loop during a second time period, and prevent the other nodes from transmitting optical signals on the second optical loop during the second time period.
However, within analogous art, Assaf Shacham et al. teaches a controller configured to schedule transmission of optical signals among the nodes through the optical network(controller set up for controlling the scheduling/timing of transmission signals taught within Page 9- Col. 1- “... When a path setup packet is sent, the gateway sets a timer to a predefined time. When the timer expires, a terminate-on time out packet is sent following the path-setup packet. The timeout packet follows the path acquired by the path-setup packet until it reaches the router where it is blocked. At that router, the path-setup packet is removed from the queue and a path-blocked packet is sent on the reverse path…” AND Page 11- Col.-2-“… a network on-chip combining a photonic circuit-switched network for high-bandwidth bulk data transmission and an electronic network which controls the photonic network while providing a medium for the exchange of short messages. The presentation covered critical design issues such as topology, routing algorithms, path-setup/teardown procedures, and deadlock avoidance rules and recovery procedures….”) . , in which the controller is configured to permit only one node to broadcast an optical signal through the first optical loop during a first time period, prevent the other nodes from transmitting optical signals on the first optical loop during the first time period ( Page 9 – Col.1 –“ …the intra-dimensional deadlock problem using path-setup timeouts. When a path setup packet is sent, the gateway sets a timer to a predefined time. When the timer expires, a terminate-on timeout packet is sent following the path-setup packet. The timeout packet follows the path acquired by the path-setup packet until it reaches the router where it is blocked. At that router, the path-setup packet is removed from the queue and a path-blocked packet is sent on the reverse path, notifying the routers that the packet was terminated and the path…”) , permit only one node to broadcast an optical signal through the second optical loop during a second time period, and prevent the other nodes from transmitting optical signals on the second optical loop during the second time period ( Page 9 – Col.1 – “…When a path-setup packet is sent, the gateway sets a timer to a predefined time.When the timer expires, a terminate-on-timeout packet is sent after the path-setup packet. The timeout packet follows the path acquired by the path-setup packet until it reaches the router where it is blocked. At that router, the path-setup packet is removed from the queue and a path-blocked packet is sent on the reverse path, notifying the routers that the packet was terminated and the path should be freed. This allows the system to recover from a potential deadlock. While this method suffers from some inefficiency because paths and gateway injection ports are blocked for some time until they are terminated without transmission, it guarantees deadlock-recovery. In an alternative method, the path-setup packet is not deadlocked but merely delayed and it reaches its destination while the timeout packet is en route. In these cases, the timeout packet reaches the destination gateway where it is ignored and discarded and the path is acquired as if the timeout has not expired….”) .
One of ordinary skill in the art would have been motivated to combine the teaching of Assaf Shacham et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. because the Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors mentioned by Assaf Shacham et al. provides a method and system for implementation of photonic circuit switching and control network within photonic networks on chip architecture.
Therefore, it would have been obvious for one in the ordinary skills in the art before the effective filing date of the claimed invention to implement the Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors mentioned by Assaf Shacham et al. within the modified teaching of the Waveguide architecture for photonic neural component with multiplexed optical signals on inter-node waveguides mentioned by Heroux et al. for implementing a system and method for photonic circuit switching and control network within photonic networks on chip architecture.
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Allowable Subject Matter
5. Claims 10,11,12,30,31,46,47 and 48 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is an examiner’s statement of reasons for objecting the claims as allowable subject matter:
As to claim 10, prior art of record does not teach or suggest the limitation mentioned within claim 10: “…a third optical path of the optical network including at least a portion fabricated in at least one layer of the integrated circuit and configured to propagate a guided mode around a closed path; and a fourth optical path of the optical network including at least a portion fabricated in at least one layer of the integrated circuit and configured to propagate a guided mode around a closed path; wherein: the third and fourth optical paths overlap with each other at a fourth set of four locations on the integrated circuit, the third optical path is coupled to two or more of the plurality of nodes at a fifth set of respective locations on the integrated circuit different from all of the locations in the first, second, third, and fourth sets of locations, and the fourth optical path is coupled to two or more of the plurality of nodes at a sixth set of respective locations on the integrated circuit different from all of the locations in the first, second, third, fourth, and fifth sets of locations.”
As to claim 11 and 12, The following claims depend objected allowable claim 10, therefore the following claims are considered objected allowable claims over prior art of record.
As to claim 30, prior art of record does not teach or suggest the limitation mentioned within claim 30: “…the controller is configured to set a first node as a transmitter during a first time period, the first node is configured to transmit an optical signal on the first optical path during the first time period, and the controller is configured to prevent the other nodes from transmitting signals on the first optical path during the first time period.”
As to claim 31, The following claims depend objected allowable claim 30, therefore the following claims are considered objected allowable claims over prior art of record.
As to claim 46, prior art of record does not teach or suggest the limitation mentioned within claim 46: “…the controller is configured to schedule a first node and a second node to communicate with each other through the first optical loop during a third time period, schedule a third node and a fourth node to communicate with each other through the second optical loop during the third time period, and prevent the other nodes from transmitting optical signals on the first and second optical loops during the third time period.”
As to claim 47, The following claims depend objected allowable claim 46, therefore the following claims are considered objected allowable claims over prior art of record.
As to claim 48, The following claims depend objected allowable claim 47, therefore the following claims are considered objected allowable claims over prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Refer to PTO-892, Notice of Reference Cited for a listing of analogous art.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OMAR S ISMAIL whose telephone number is (571)272-9799 and Fax # is (571)273-9799. The examiner can normally be reached on M-F 9:00am-6:00pm.
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/OMAR S ISMAIL/
Primary Examiner, Art Unit 2635