DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/01/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claim 1 recites “ a plurality of semiconductor devices is mounted” (in lines 1-2) is replete with grammatical error.
Claims 1, 5 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " the conductive spacer " in line 9. There is insufficient antecedent basis for this limitation in the claim. NOTE: In line 5, the applicants claim “a plurality of conductive spacers”; thus, the Examiner suggests to amend “one of the plurality of conductive spacers”.
Claim 5 recites the limitation " the conductive spacer " in line 11. There is insufficient antecedent basis for this limitation in the claim. NOTE: In line 7, the applicants claim “a plurality of conductive spacers”; thus, the Examiner suggests to amend “one of the plurality of conductive spacers”.
Claim 11 recites the limitation " the conductive spacer " in line 7. There is insufficient antecedent basis for this limitation in the claim. NOTE: In line 4, the applicants claim “a plurality of conductive spacers”; thus, the Examiner suggests to amend “one of the plurality of conductive spacers”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over KR 10-1956996 (Hereafter KR reference), and further in view of Hirotsuru (US 20200373251).
Regarding claim 1, KR reference teaches a ceramic substrate (25) for a power module (see fig. 1) on which a plurality of semiconductor devices (31/32) is mounted (see fig. 1), the ceramic substrate (25) comprising:
a ceramic base (25);
a metal layer pattern (21/22/23) formed on at least one surface of the ceramic base (125);
a plurality of conductive spacers (41,42,43,44) each having one surface (refer to the bottom surfaces of 42 and 44) bonded to the metal layer pattern (21 and 23); and
a solder layer (70) configured to bond the metal layer pattern (21 and 23) and the one surface of each of the conductive spacers (42/44).
wherein the conductive spacer (41/43) is disposed to be bonded to an electrode of the semiconductor device (31 or 32) (see fig. 1).
KR reference does not show teach a brazing filler layer configured to brazing-bond the metal layer pattern and the one surface of each of the conductive spacers.
Hirotsuru teaches the same field of an endeavor wherein using an active metal brazing method to bonding the metal layers and ceramic layer (see pars. 48 and 56).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a brazing method as taught by Hirotsuru in the teaching of KR reference such that a brazing filler layer configured to brazing-bond the metal layer pattern and the one surface of each of the conductive spacers because it balances the thermal expansion properties with effective heat dissipation for power module (see par. 48).
Regarding claim 3, KR reference and Hirotsuru teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, KR reference teaches the conductive spacer (41/42/43/44) is formed of at least one of Cu, Mo, a CuMo alloy, and a CuW alloy.
Regarding claim 4, KR reference and Hirotsuru teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Hirotsuru teaches the brazing filler layer is made of a material comprising at least one of Ag, Cu, AgCu, and AgCuTi (see par. 56).
Regarding claim 5, KR reference teaches a power module comprising:
a pair of ceramic substrates (14 and 25) in each of which a metal layer pattern (21/22/23) has been formed on at least one surface of a ceramic base (25); and
a plurality of semiconductor devices (31 and 32) disposed between the pair of ceramic substrates (14 and 25), wherein each of the pair of ceramic substrates comprises:
a plurality of conductive spacers (41/42/43/44) each having one surface (refer to bottom surface of 42 and 44) bonded to the metal layer pattern (21/22/23);
a bonding layer (70) configured to bond the metal layer pattern (21 and 23) and the one surface of each of the conductive spacers (42/44); and
wherein the conductive spacer (41/43) provided in at least one of the pair of ceramic substrates (14/25) is bonded to an electrode of the semiconductor device (31/32) (see fig. 1).
KR reference does not show teach a brazing filler layer configured to brazing-bond the metal layer pattern and the one surface of each of the conductive spacers.
Hirotsuru teaches the same field of an endeavor wherein using an active metal brazing method to bonding the metal layers and ceramic layer (see pars. 48 and 56).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the active metal brazing method as taught by Hirotsuru in the teaching of KR reference such that a brazing filler layer configured to brazing-bond the metal layer pattern and the one surface of each of the conductive spacers because it balances the thermal expansion properties with effective heat dissipation for power module (see par. 48).
Regarding claim 10, KR reference and Hirotsuru teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, KR reference teaches the electrode (22/23) of each of the semiconductor devices (31/32) is bonded to the other surface of each of the conductive spacers by a bonding layer comprising a solder or Ag paste (70) (see fig. 1).
Regarding claim 11, KR reference teaches a method of manufacturing a ceramic substrate for a power module on which a plurality of semiconductor devices is mounted in fig. 1, the method comprising:
forming a metal layer pattern (21,22,23) on at least one surface of a ceramic base (25);
preparing a plurality of conductive spacers (41,42,43,44); and
a solder layer (70) configured to bond the metal layer pattern (21 and 23) and the one surface of each of the conductive spacers (42/44); and
wherein the conductive spacer (41/43) provided in at least one of the pair of ceramic substrates (14/25) is bonded to an electrode of the semiconductor device (31/32) via the solder layer (70) (see fig. 1).
KR reference does not show teach a brazing filler layer configured to brazing-bond the metal layer pattern and the one surface of each of the conductive spacers, wherein the brazing-bonding comprises disposing the conductive spacer so that the conductive spacer is bonded to an electrode of the semiconductor device.
Hirotsuru teaches the same field of an endeavor wherein using an active metal brazing method to bonding the metal layers and ceramic layer (see pars. 48 and 56).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the active metal brazing method as taught by Hirotsuru in the teaching of KR reference such that a brazing filler layer configured to brazing-bond the metal layer pattern and the one surface of each of the conductive spacers, wherein the brazing-bonding comprises disposing the conductive spacer so that the conductive spacer is bonded to an electrode of the semiconductor device because it balances the thermal expansion properties with effective heat dissipation for power module (see par. 48).
Regarding claim 12, KR reference and Hirotsuru teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, KR reference teaches in the preparing of the plurality of conductive spacers, the conductive spacer is formed of at least one of Cu, Mo, a CuMo alloy, and a CuW alloy.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the metal layer pattern comprises a first metal layer pattern formed on a top surface of the ceramic base and a second metal layer pattern formed on a bottom surface of the ceramic base, and the conductive spacer comprises a plurality of first conductive spacers each having one surface bonded to the first metal layer pattern and a plurality of second conductive spacers each having one surface bonded to the second metal layer pattern.”
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the metal layer pattern comprises a first metal layer pattern formed on a top surface of the ceramic base and a second metal layer pattern formed on a bottom surface of the ceramic base, and the conductive spacer comprises a plurality of first conductive spacers each having one surface bonded to the first metal layer pattern and a plurality of second conductive spacers each having one surface bonded to the second metal layer pattern.” Claims 7-9 include all the limitations of claim 6.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the brazing-bonding further comprises: disposing a brazing filler layer having a thickness of 5 µm or more to 100 µm or less between the one surface of each of the conductive spacers and the metal layer pattern by using any one method of paste coating, foil attachment, and a P-filler; and brazing the brazing filler layer by melting the brazing filler layer.” Claims 14 and 15 include all the limitations of claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
Prosecution Insights