Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on March 01, 2024, April 05, 2024, and February 09, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed February 10, 2026 has been entered. Claims 1-14 remain pending in the application. Claims 1-3, 5-9 & 13-14 are amended. Applicant’s amendments to the Claims did not need to overcome any objection(s) and/or 35 U.S.C. § 112(b) rejection(s) previously set forth in the Non-Final Office Action mailed November 14, 2025, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments, see pp. 5-9 of applicant’s remarks, filed February 10, 2026, that the prior art reference with respect to the rejection(s) of amended independent claim(s) 1 & 6, under U.S.C. § 102(a)(1), Sugiyama (US 2021/0270698 A1, hereinafter, Sugiyama), have been fully considered but they are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sugiyama, in view of Novack et al. (US 2017/0082799 A1, hereinafter, Novack), and further in view of Cho et al. (US 2020/0124792 A1, hereinafter, Cho). Therefore, the rejections of amended independent claims 1 & 6, and dependent claims 2-5 & 7-14, which depend from and incorporate the limitations of amended independent claims 1 & 6, are respectively maintained. Updated rejections based on amended features follow.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 8, 9, 11-12 & 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 3, 8, 9, & 14, recite “and the region to be removed by dicing has a width of 100 µm or less” in ll. 3-4, where the “width of 100 µm or less” is not disclosed in the specification. Specification mentions “100 pam” and “100 pym”, which are different units, and doesn’t mention being less than 100 µm. Claims 11-12 are rejected based on dependency on claims 3 & 9, which do not rectify the defect.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, & 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 2021/0270698 A1, Pub. Date Sep. 2, 2021, hereinafter, Sugiyama), in view of Novack et al. (US 2017/0082799 A1, Pub. Date Mar. 23, 2017, hereinafter, Novack), and further in view of Cho et al. (US 2020/0124792 A1, Pub. Date Apr. 23, 2020, hereinafter Cho).
Regarding independent claim 1, Sugiyama, teaches:
An inspection optical circuit for inspecting a tested circuit formed on an optical circuit chip on a wafer (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018], [0021], [0031], [0037] & [0058]: optical device (chip 110) includes optical circuits (e.g., 90° optical hybrids 140a/140b), testing is performed using a testing optical waveguide)
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Sugiyama, is silent in regard to:
by inputting and outputting light through an optical path converter, wherein the optical path converter is formed in a region to be polished and reduced by polishing on the same optical circuit chip as the tested circuit, and
a folded waveguide for connecting an input/output of the tested circuit and the optical path converter is formed in both the region to be polished and reduced by polishing and a region to be removed by dicing, wherein the folded waveguide is removed by dicing and polishing.
However, Novack, further teaches:
by inputting and outputting light through an optical path converter ([0073]-[0074]: grating coupler acts as the optical path converter for the inspection circuit), wherein the optical path converter is formed in a region to be polished and reduced by polishing on the same optical circuit chip as the tested circuit ([0073]-[0074] & [0079]: optical path converter is located in a region reduced/removed by polishing), and
It would have been obvious to one of ordinary skill in the art at the time the invention was made to configure the wafer-level testing apparatus of Sugiyama/Novack by routing the testing optical waveguide so that it overlaps or crosses the scribe/dicing line, and is removed by dicing and polishing, according to known methods. A POSITA would have been motivated to arrange the folded waveguide across the dicing line, as suggested by Novack, because placing the sacrificial testing components on opposite sides of the saw line ensures that the routine step of separating the chips simultaneously destroys the temporary test optical paths. This optimizes the layout of the wafer by pushing components into or across the disposable dicing lanes, maximizing the usable area for the primary tested circuits, and yield predictable results (KSR).
However, Novack, in combination with Cho, further teach:
a folded waveguide for connecting an input/output of the tested circuit and the optical path converter is formed in both the region to be polished and reduced by polishing and a region to be removed by dicing (Disclosed in combination: Novack: [0073]-[0074]: mentions the test waveguide 180 connecting the grating coupler 150 to the edge coupler 140, and notes dicing lanes 160 are provided to so the sacrificial region 115 can be cut out; Cho: [0050]), wherein the folded waveguide is removed by dicing and polishing (Disclosed in combination: Novack: [0079]: mentions dicing lanes 160 are provided to so the sacrificial region 115 can be cut out; Cho: [0050]-[0051]: combining these teachings (Novack and Cho) covers removal by both dicing and polishing).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the wafer-level testing apparatus of Sugiyama/Novack by routing the testing optical waveguide so that it overlaps or crosses the scribe/dicing line, as taught by Cho, according to known methods. A POSITA would be motivated to make this modification to optimize wafer real estate and streamline the manufacturing process. By routing the sacrificial test waveguide across the dicing lanes, the manufacturer ensures that the standard wafer singulation (dicing) process automatically severs the physical and optical connection between the test structures and the primary circuit. This eliminates the need for additional, removal or etching step(s), isolates the operational optic transmitter and receiver post-test, prevents any residual test signals or reflection from interfering with the final commercial chip’s performance, and yield predictable results (KSR).
Novack, is silent in regard to:
wherein a folded region of the folded waveguide is provided on a dicing line for cutting out the optical circuit chip,
However, Sugiyama, in combination with Cho, further teach:
wherein a folded region of the folded waveguide is provided on a dicing line for cutting out the optical circuit chip (Disclosed in combination: Sugiyama: [0059]; Cho: [0050]-[0051]),
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the wafer-level testing apparatus of Sugiyama/Novack by routing the testing waveguide across the dicing/scribe lines as taught by Cho and Sugiyama, according to known methods. The motivation to combine these teachings is to optimize wafer real estate and ensure that all temporary testing structures (waveguides and optical path converters) are destroyed or removed during the standard die singulation (dicing) and facet preparation (polishing) phases, eliminated the need for removal steps and minimizing optical loss in the final product, yielding predictable results (KSR).
Regarding dependent claim 2, Sugiyama, teaches:
The inspection optical circuit according to claim 1 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037] & [0058]),
Sugiyama, is silent in regard to:
wherein the optical path converter is formed in the region to be polished and reduced by polishing after the region to be removed by dicing is cut off by dicing along the dicing line.
However, Novack, further teaches:
wherein the optical path converter is formed in the region to be polished and reduced by polishing ([0073]-[0074] & [0079]: test grating coupler acts as the optical path converter and is located in the region reduced/removed by polishing)
It would have been obvious to one of ordinary skill in the art at the time the invention was made to sequence the removal of the testing interfaces such that the optical path converted is polished away after the chip is cut along the dicing line, as taught by Novack, according to known methods. Novack teaches that the testing interface (e.g., the test grating coupler) can be removed via polishing during facet preparation. A POSITA would recognize that standard semiconductor and photonic integrated circuit manufacturing dictates that wafer singulation (dicing or cleaving) occurs before the individual die facet preparation (polishing). By first cutting the wafer into discrete chips to expose the raw edge facet before polishing that specific edge to achieve optical-grade smoothness. Therefore, modifying the process to ensure dicing happens prior to polishing that removes the optical path converter is the application of known industry techniques to yield predictable manufacturing results (KSR).
However, Novack, in combination with Cho, further teach:
after the region to be removed by dicing is cut off by dicing along the dicing line (Disclosed in combination: Novack: [0078]-[0079]; Cho: [0034]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the testing and facet preparation techniques of Novack with the wafer-level testing and dicing sequence of Cho, according to known methods. Novack teaches that the testing interface (e.g., the test grating coupler) can be removed via polishing during facet preparation. Cho teaches conducting wafer-level testing prior to individual chip separation, followed by a specific step where “a sawing or dicing process may be performed along the scribe line 20” to separate the semiconductor substrate into chip regions and cut the test waveguide. A POSITA would have been motivated to combine Cho’s dicing step with Novack’s polishing step in this sequential order. A POSITA would understand that it is physically impossible to polish the edge facet of a chip while it remains embedded within the continuous semiconductor wafer. Therefore, one would be motivated to first apply Cho’s teaching of dicing the wafer along the scribe lines to singulate (dicing or cleaving) the chips and expose their edges, and then apply Novack’s teaching of polishing the facet to remove sacrificial testing components and achieve optical-grade smoothness. This combination represents the predictable application of known semiconductor singulation and polishing techniques to achieve the expected result (KSR) of an operational, efficient photonic chip stripped of temporary test structures.
Regarding dependent claim 3, Sugiyama, teaches:
The inspection optical circuit according to claim 1 (Figs. 1, 2, & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037]-[0040], [0058] & [0073]-[0074]),
Sugiyama, is silent in regard to:
wherein the dicing line is a groove formed on the wafer, and the region to be removed by dicing is a region where the groove is not dug, and the region to be removed by dicing has a width of 100 µm or less.
However, Novack, further teaches:
wherein the dicing line is a groove formed on the wafer ([0079] & [0086]: uses an etch trench, which serves as the groove defining the separation line between the chips), and the region to be removed by dicing is a region where the groove is not dug ([0079]: teaches that the physical saw line/cleave line goes through the material spanning between the couplers, and the dicing blade removes the remaining material/gap region associated with the trench), and the region to be removed by dicing has a width of 100 µm or less ([0081]: the gap defines the width of the trench/dicing lane separating the operational chip and the sacrificial testing region).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to configure the dicing line as the groove (trench) and restrict the removal region to a width of 100 µm or less, based on the teachings of Novack, according to known methods. Novack teaches testing across an etched trench where the gap between the tested edge coupler and the sacrificial test coupler is between 50 and 100 µm. A POSITA would understand that this gap defines the physical dicing lane or separation region that will be cut, cleaved, or polished away to singulate the chip. A POSITA would have been motivated to implement this trench geometry and narrow width to achieve two predictable goals: optical efficiency as stated by Novack [0081], maintaining a small gap minimizes optical divergence across the trench, ensuring accurate wafer-level testing with minimal coupling loss before the chips are separated. The second goal dealing with wafer real estate optimization, minimizing the width of the dicing trench to 100 µm or less maximizes the number of photonic integrated circuits that can be fabricated on a single wafer, which is a standard motivation in semiconductor and photonic manufacturing, and yield predictable results (KSR).
Regarding dependent claim 5, Sugiyama, teaches:
The inspection optical circuit according to claim 1 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021]-[0023], [0029], [0031], [0033], [0037], [0057]-[0058] & [0062]),
Sugiyama, is silent in regard to:
wherein the dicing line is a groove formed on the wafer, and the region to be removed by dicing is separated from the optical circuit chip by the groove.
However, Novack, further teaches:
wherein the dicing line is a groove formed on the wafer ([0079] & [0086]: an etch trench is structurally synonymous with a groove formed on a wafer, defining the separation line), and the region to be removed by dicing is separated from the optical circuit chip by the groove ([0073] & [0086]: teaches that the sacrificial region/region to be removed is physically separated from the main optical circuit chip by the dicing lane which is configured as an etched trench/groove).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the wafer-level testing configuration of Sugiyama/Novack/Cho such that the dicing line is formed as an etched groove (trench) that separates the region to be removed from the optical circuit chip, as taught by Novack, according to known methods. A POSITA would have been motivated to implement the etch trench taught by Novack to physically separate the sacrificial testing region from the functional chip prior to the final dicing step. Etching a trench between the testing edge couplers and the functional edge couplers removes dense semiconductor material from the vicinity of the delicate optical facets. A POSITA would understand that creating the separating groove provides a physical guide for the dicing process (establishing the dicing line) and relives mechanical stress during the mechanical separation of the chips. This prevents micro-cracking or chipping from propagating into the optical circuit chip during the removal of the sacrificial region, increasing manufacturing yield and ensuring integrity of the optical facets, thus yielding predictable results (KSR).
Regarding independent claim 6, Sugiyama, teaches:
A method for manufacturing a plurality of optical circuit chips including a tested circuit on a wafer, the method comprising (Figs. 1, 5, 6 & 7; [0003]-[0005], [0018]-[0019], [0023], [0038]-[0040] & [0073]-[0074]):
wherein a folded region of the folded waveguide is provided on a dicing line for cutting out the optical circuit chip ([0059]);
Sugiyama, is silent in regard to:
forming an optical path converter in a region to be polished and reduced by polishing on the same optical circuit chip as the tested circuit;
removing a remaining part of the optical path converter and the folded waveguide by polishing after the dicing.
However, Novack, further teaches:
forming an optical path converter in a region to be polished and reduced by polishing on the same optical circuit chip as the tested circuit ([0079]: the test grating coupler is the optical path converter, teaches forming it in the area targeted for polishing reduction);
removing a remaining part of the optical path converter and the folded waveguide by polishing after the dicing ([0078]-[0079]: the sequential combination of these lines confirms the test structures are removed by polishing following the dicing operation).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the wafer-level testing and dicing method of Sugiyama and Cho by incorporating the specific facet preparation and structure-removal polishing step taught by Novack, according to known methods. A POSITA would have been motivated to combine the polishing removal step with the testing and dicing sequence of Sugiyama and Cho to maximize manufacturing efficiency. In photonic integrated circuit fabrication, creating smooth edge faces is a mandatory requirement to minimize optical insertion loss for the final commercial chip. A POSITA would recognize that since the chip’s edge must be polished after the dicing step cuts the folded waveguide, they can place the optical path converter in this polishing region, as suggested by Novack. The motivation is to achieve two manufacturing goals simultaneously: (1) achieving the necessary optical-grade smoothness on the chip’s functional facet, and (2) remove the remnants of the sacrificial folded waveguide and the optical path converter. By adopting Novack’s polishing step, the manufacturer eliminates the temporary test structures during a routine, facet-preparation process, avoiding the need for an expensive, separate etching or removal step for the test components. This combination is a predictable use of standard photonic manufacturing techniques to streamline production and reduce costs, and yield predictable results (KSR).
Sugiyama, in combination with Novack, are silent in regard to:
forming a folded waveguide for connecting an input/output waveguide of the tested circuit and the optical path converter in both the region to be polished and reduced by polishing and a region to be removed by dicing,
dicing along the dicing line after the tested circuit is inspected; and
However, Sugiyama, in combination with Cho, further teach:
dicing along the dicing line after the tested circuit is inspected (Disclosed in combination: Sugiyama: [0038]; Cho: [0034]); and
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the wafer-level testing layout of Sugiyama with the specific testing and dicing sequence of Cho, according to known methods. A POSITA would have been motivated to combine Sugiyama’s structural layout with Cho’s method steps to establish an efficient, streamlined manufacturing workflow. A POSITA would understand that testing individual, singulated chips is time-consuming and risks damaging delicate optical facets. Therefore, one would be motivated to adopt Cho’s sequence of operations, testing the circuit and subsequently dicing along the specific line where the folded waveguide crosses, to effectively utilize Sugiyama’s wafer-level design. This combination yields the predictable and desirable result (KSR) of simultaneously separating the chips for commercial use and automatically sever the temporary testing connections during routine wafer singulation, eliminating the need for a separate, costly waveguide-removal step.
However, Novack, in combination with Cho, further teach:
forming a folded waveguide for connecting an input/output waveguide of the tested circuit and the optical path converter in both the region to be polished and reduced by polishing and a region to be removed by dicing (Disclosed in combination: Novack: [0073]-[0074]: mentions the test waveguide 180 connecting the grating coupler 150 to the edge coupler 140, and mentions dicing lanes 160 are provided to so the sacrificial region 115 can be cut out; Cho: [0050]),
It would have been obvious to one of ordinary skill in the art at the time the invention was made to implement the manufacturing method of Sugiyama, integrated with the wafer-level dicing techniques of Cho, and further modified by the specific testing structure removal process taught by Novack, according to known methods. A POSITA would be motivated to utilize the sequence of inspecting the circuit, dicing the wafer along the lines where the test waveguide cross (as taught by Sugiyama and Cho), and subsequently polishing the facet to remove the remaining optical path converter, as taught by Novack. In standard photonic integrated circuit manufacturing, individual die facet preparation (polishing) physically requires the wafer to be singulated (diced) first to expose raw chip edges. A POSITA would combine these steps to streamline the manufacturing flow, ensuring that routine chip singulation and edge facet optical smoothing simultaneously eliminate the sacrificial wafer-level testing interfaces, saving dedicated etching steps and maximizing final chip performance, yielding predictable results (KSR).
Regarding dependent claim 7, Sugiyama, teaches:
The method according to claim 6 (Figs. 1, 5, 6 & 7; [0003]-[0005], [0018]-[0019], [0023], [0031], [0038]-[0040] & [0073]-[0074]),
Sugiyama, is silent in regard to:
wherein the optical path converter is formed in the region to be polished and reduced by polishing after the region to be removed by dicing is cut off by dicing along the dicing line.
However, Novack, further teaches:
wherein the optical path converter is formed in the region to be polished and reduced by polishing ([0073]-[0074] & [0079]: test grating coupler acts as the optical path converter and is located in the region reduced/removed by polishing)
It would have been obvious to one of ordinary skill in the art at the time the invention was made to sequence the removal of the testing interfaces such that the optical path converted is polished away after the chip is cut along the dicing line, as taught by Novack, according to known methods. Novack teaches that the testing interface (e.g., the test grating coupler) can be removed via polishing during facet preparation. A POSITA would recognize that standard semiconductor and photonic integrated circuit manufacturing dictates that wafer singulation (dicing or cleaving) occurs before the individual die facet preparation (polishing). By first cutting the wafer into discrete chips to expose the raw edge facet before polishing that specific edge to achieve optical-grade smoothness. Therefore, modifying the process to ensure dicing happens prior to polishing that removes the optical path converter is the application of known industry techniques to yield predictable manufacturing results (KSR).
However, Novack, in combination with Cho, further teach:
after the region to be removed by dicing is cut off by dicing along the dicing line (Disclosed in combination: Novack: [0078]-[0079]; Cho: [0034]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the testing and facet preparation techniques of Novack with the wafer-level testing and dicing sequence of Cho, according to known methods. Novack teaches that the testing interface (e.g., the test grating coupler) can be removed via polishing during facet preparation. Cho teaches conducting wafer-level testing prior to individual chip separation, followed by a specific step where “a sawing or dicing process may be performed along the scribe line 20” to separate the semiconductor substrate into chip regions and cut the test waveguide. A POSITA would have been motivated to combine Cho’s dicing step with Novack’s polishing step in this sequential order. A POSITA would understand that it is physically impossible to polish the edge facet of a chip while it remains embedded within the continuous semiconductor wafer. Therefore, one would be motivated to first apply Cho’s teaching of dicing the wafer along the scribe lines to singulate (dicing or cleaving) the chips and expose their edges, and then apply Novack’s teaching of polishing the facet to remove sacrificial testing components and achieve optical-grade smoothness. This combination represents the predictable application of known semiconductor singulation and polishing techniques to achieve the expected result (KSR) of an operational, efficient photonic chip stripped of temporary test structures.
Regarding dependent claim 8, Sugiyama, teaches:
The method according to claim 6 (Figs. 1, 5, 6 & 7; [0003]-[0005], [0018]-[0019], [0023], [0031], [0038]-[0040] & [0073]-[0074]),
Sugiyama, is silent in regard to:
wherein the dicing line is a groove formed on the wafer, and the region to be removed by dicing is a region where the groove is not dug, and the region to be removed by dicing has a width of 100 µm or less.
However, Novack, further teaches:
wherein the dicing line is a groove formed on the wafer ([0079] & [0086]: uses an etch trench, which serves as the groove defining the separation line between the chips), and the region to be removed by dicing is a region where the groove is not dug ([0079]: teaches that the physical saw line/cleave line goes through the material spanning between the couplers, and the dicing blade removes the remaining material/gap region associated with the trench), and the region to be removed by dicing has a width of 100 µm or less ([0081]: the gap defines the width of the trench/dicing lane separating the operational chip and the sacrificial testing region).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to configure the dicing line as the groove (trench) and restrict the removal region to a width of 100 µm or less, based on the teachings of Novack, according to known methods. Novack teaches testing across an etched trench where the gap between the tested edge coupler and the sacrificial test coupler is between 50 and 100 µm. A POSITA would understand that this gap defines the physical dicing lane or separation region that will be cut, cleaved, or polished away to singulate the chip. A POSITA would have been motivated to implement this trench geometry and narrow width to achieve two predictable goals: optical efficiency as stated by Novack [0081], maintaining a small gap minimizes optical divergence across the trench, ensuring accurate wafer-level testing with minimal coupling loss before the chips are separated. The second goal dealing with wafer real estate optimization, minimizing the width of the dicing trench to 100 µm or less maximizes the number of photonic integrated circuits that can be fabricated on a single wafer, which is a standard motivation in semiconductor and photonic manufacturing, and yield predictable results (KSR).
Regarding dependent claim 9, Sugiyama, teaches:
The inspection optical circuit according to claim 2 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037]-[0040], [0058] & [0073]-[0074]),
Sugiyama, is silent in regard to:
wherein the dicing line is a groove formed on the wafer, and the region to be removed by dicing is a region where the groove is not dug, and the region to be removed by dicing has a width of 100 µm or less.
However, Novack, further teaches:
wherein the dicing line is a groove formed on the wafer ([0079] & [0086]: uses an etch trench, which serves as the groove defining the separation line between the chips), and the region to be removed by dicing is a region where the groove is not dug ([0079]: teaches that the physical saw line/cleave line goes through the material spanning between the couplers, and the dicing blade removes the remaining material/gap region associated with the trench), and the region to be removed by dicing has a width of 100 µm or less ([0081]: the gap defines the width of the trench/dicing lane separating the operational chip and the sacrificial testing region).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to configure the dicing line as the groove (trench) and restrict the removal region to a width of 100 µm or less, based on the teachings of Novack, according to known methods. Novack teaches testing across an etched trench where the gap between the tested edge coupler and the sacrificial test coupler is between 50 and 100 µm. A POSITA would understand that this gap defines the physical dicing lane or separation region that will be cut, cleaved, or polished away to singulate the chip. A POSITA would have been motivated to implement this trench geometry and narrow width to achieve two predictable goals: optical efficiency as stated by Novack [0081], maintaining a small gap minimizes optical divergence across the trench, ensuring accurate wafer-level testing with minimal coupling loss before the chips are separated. The second goal dealing with wafer real estate optimization, minimizing the width of the dicing trench to 100 µm or less maximizes the number of photonic integrated circuits that can be fabricated on a single wafer, which is a standard motivation in semiconductor and photonic manufacturing, and yield predictable results (KSR).
Regarding dependent claim 13, Sugiyama, teaches:
The inspection optical circuit according to claim 2 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021]-[0023], [0029], [0031], [0033], [0037]-[0040], [0057]-[0058] & [0062]),
Sugiyama, is silent in regard to:
wherein the dicing line is a groove formed on the wafer, and the region to be removed by dicing is separated from the optical circuit chip by the groove.
However, Novack, further teaches:
wherein the dicing line is a groove formed on the wafer ([0079] & [0086]: uses an etch trench, which serves as the groove defining the separation line between the chips), and the region to be removed by dicing is separated from the optical circuit chip by the groove ([0073]-[0074] & [0086]: demonstrates that the sacrificial region to be removed is physically separated from the main optical circuit chip by the dicing lane, which takes the form of the etches trench/groove).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the wafer-level testing configuration of the primary combination, Sugiyama/Novack/Cho, such that the dicing line is formed as an etched groove (trench) that physically separates the region to be removed from the optical circuit chip, as taught by Novack, according to known methods. A POSITA would have been motivated to implement the etch trench taught by Novack to define the dicing line and physically separate the sacrificial testing region from the functional chip prior to the final mechanical dicing step. Etching a trench between the testing edge couplers and the functional edge couplers removes semiconductor material from the vicinity of the delicate optical facets. A POSITA would understand that creating a separating groove provides a physical guide for the dicing process (establishing the dicing line) and relives mechanical stress during the physical separation of the chips. Preventing micro-cracking, chipping, or mechanical shock from propagating into the functional optical circuit chip during the removal of the sacrificial region, increasing manufacturing yield and ensuring the structural integrity of the final optical facets, yielding predictable results (KSR).
Regarding dependent claim 14, Sugiyama, teaches:
The method according to claim 7 (Figs. 1, 5, 6 & 7; [0003]-[0005], [0018]-[0019], [0023], [0031], [0038]-[0040] & [0073]-[0074]),
Sugiyama, is silent in regard to:
wherein the dicing line is a groove formed on the wafer, and the region to be removed by dicing is a region where the groove is not dug, and the region to be removed by dicing has a width of 100 µm or less.
However, Novack, further teaches:
wherein the dicing line is a groove formed on the wafer ([0079] & [0086]: uses an etch trench, which serves as the groove defining the separation line between the chips), and the region to be removed by dicing is a region where the groove is not dug ([0079]: teaches that the physical saw line/cleave line goes through the material spanning between the couplers, and the dicing blade removes the remaining material/gap region associated with the trench), and the region to be removed by dicing has a width of 100 µm or less ([0081]: the gap defines the width of the trench/dicing lane separating the operational chip and the sacrificial testing region).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to configure the dicing line as the groove (trench) and restrict the removal region to a width of 100 µm or less, based on the teachings of Novack, according to known methods. Novack teaches testing across an etched trench where the gap between the tested edge coupler and the sacrificial test coupler is between 50 and 100 µm. A POSITA would understand that this gap defines the physical dicing lane or separation region that will be cut, cleaved, or polished away to singulate the chip. A POSITA would have been motivated to implement this trench geometry and narrow width to achieve two predictable goals: optical efficiency as stated by Novack [0081], maintaining a small gap minimizes optical divergence across the trench, ensuring accurate wafer-level testing with minimal coupling loss before the chips are separated. The second goal dealing with wafer real estate optimization, minimizing the width of the dicing trench to 100 µm or less maximizes the number of photonic integrated circuits that can be fabricated on a single wafer, which is a standard motivation in semiconductor and photonic manufacturing, and yield predictable results (KSR).
Claims 4 & 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama, in view of Traverso et al. (US 2018/0313718 A1, Pub. Date Nov. 1, 2018, hereinafter Traverso), in view of Novack, and further in view of Cho.
Regarding dependent claim 4, Sugiyama, teaches:
The inspection optical circuit according to claim 1 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037]-[0040], [0058], [0062] & [0073]-[0074]), wherein the input/output waveguide of the tested circuit and the folded waveguide are connected (Figs. 1 & 2; [0033]-[0034], [0041], [0064] & [Claim 3])
Sugiyama, is silent in regard to:
via a spot-size converter including a tapered waveguide.
However, Traverso, further teaches:
via a spot-size converter including a tapered waveguide (Figs. 11A & 11B; [0015], [0034], [0064], [0068], [0070] & [Claim 1]: discloses edge couplers 225 A/B that function as optical couplers and “each comprises at least one tapered waveguide configured to adjust a diameter of a mode of the first optical signal”).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate via a spot-size converter including a tapered waveguide, of Traverso to Sugiyama, in order to attain and improve Sugiyama’s inspection circuit, where Sugiyama’s goal is to provide a low-labor efficient method for testing optical circuits on a wafer prior to dicing, Traverso teaches an optical coupling mechanism, an edge coupler 225 featured a tapered waveguide, whose function is to “adjust a diameter of a mode” to transfer an optical signal, teaching using tapered waveguides for efficient optical coupling and mode matching between structures, where the use of a spot-size converter (SSC) is a well-known and predictable technique in silicon photonics to reduce coupling loss and efficiently match modes between waveguides and different dimensions (such as connecting a temporary larger, testing waveguide to a dense, smaller core waveguide), a PHOSITA would recognize the benefit of using a low-loss, mode-matching SSC to replace or enhance the general coupling mechanism in Sugiyama’s testing path, improving the efficiency and accuracy of the optical inspection circuit and optimizing performance and minimizing insertion loss, by substituting Sugiyama’s general coupler with the specific SSC/tapered waveguide from Traverso, an obvious design choice to achieve the predictable results of improved coupling efficiency in the wafer testing configuration.
Regarding dependent claim 10, Sugiyama, teaches:
The inspection optical circuit according to claim 2 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037]-[0040], [0058], [0062] & [0073]-[0074]), wherein the input/output waveguide of the tested circuit and the folded waveguide are connected (Figs. 1 & 2; [0033]-[0034], [0041], [0064] & [Claim 3])
Sugiyama, is silent in regard to:
via a spot-size converter including a tapered waveguide.
However, Traverso, further teaches:
via a spot-size converter including a tapered waveguide (Figs. 11A & 11B; [0015], [0034], [0064], [0068], [0070] & [Claim 1]: discloses edge couplers 225 A/B that function as optical couplers and “each comprises at least one tapered waveguide configured to adjust a diameter of a mode of the first optical signal”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate via a spot-size converter including a tapered waveguide, of Traverso to Sugiyama, in order to attain and improve Sugiyama’s inspection circuit, where Sugiyama’s goal is to provide a low-labor efficient method for testing optical circuits on a wafer prior to dicing, Traverso teaches an optical coupling mechanism, an edge coupler 225 featured a tapered waveguide, whose function is to “adjust a diameter of a mode” to transfer an optical signal, teaching using tapered waveguides for efficient optical coupling and mode matching between structures, where the use of a spot-size converter (SSC) is a well-known and predictable technique in silicon photonics to reduce coupling loss and efficiently match modes between waveguides and different dimensions (such as connecting a temporary larger, testing waveguide to a dense, smaller core waveguide), a PHOSITA would recognize the benefit of using a low-loss, mode-matching SSC to replace or enhance the general coupling mechanism in Sugiyama’s testing path, improving the efficiency and accuracy of the optical inspection circuit and optimizing performance and minimizing insertion loss, by substituting Sugiyama’s general coupler with the specific SSC/tapered waveguide from Traverso, an obvious design choice to achieve the predictable results of improved coupling efficiency in the wafer testing configuration
Regarding dependent claim 11, Sugiyama, teaches:
The inspection optical circuit according to claim 3 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037]-[0040], [0058], [0062] & [0073]-[0074]), wherein the input/output waveguide of the tested circuit and the folded waveguide are connected (Figs. 1 & 2; [0033]-[0034], [0041], [0064] & [Claim 3])
Sugiyama, is silent in regard to:
via a spot-size converter including a tapered waveguide.
However, Traverso, further teaches:
via a spot-size converter including a tapered waveguide (Figs. 11A & 11B; [0015], [0034], [0064], [0068], [0070], & [Claim 1]: discloses edge couplers 225 A/B that function as optical couplers and “each comprises at least one tapered waveguide configured to adjust a diameter of a mode of the first optical signal”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate via a spot-size converter including a tapered waveguide, of Traverso to Sugiyama, in order to attain and improve Sugiyama’s inspection circuit, where Sugiyama’s goal is to provide a low-labor efficient method for testing optical circuits on a wafer prior to dicing, Traverso teaches an optical coupling mechanism, an edge coupler 225 featured a tapered waveguide, whose function is to “adjust a diameter of a mode” to transfer an optical signal, teaching using tapered waveguides for efficient optical coupling and mode matching between structures, where the use of a spot-size converter (SSC) is a well-known and predictable technique in silicon photonics to reduce coupling loss and efficiently match modes between waveguides and different dimensions (such as connecting a temporary larger, testing waveguide to a dense, smaller core waveguide), a PHOSITA would recognize the benefit of using a low-loss, mode-matching SSC to replace or enhance the general coupling mechanism in Sugiyama’s testing path, improving the efficiency and accuracy of the optical inspection circuit and optimizing performance and minimizing insertion loss, by substituting Sugiyama’s general coupler with the specific SSC/tapered waveguide from Traverso, an obvious design choice to achieve the predictable results of improved coupling efficiency in the wafer testing configuration.
Regarding dependent claim 12, Sugiyama, teaches:
The inspection optical circuit according to claim 9 (Figs. 1, 2 & 3; [Abstract], [0003]-[0005], [0018]-[0019], [0021], [0023], [0031], [0037]-[0040], [0058], [0062] & [0073]-[0074]), wherein the input/output waveguide of the tested circuit and the folded waveguide are connected (Figs. 1 & 2; [0033]-[0034], [0041], [0064] & [Claim 3])
Sugiyama, is silent in regard to:
via a spot-size converter including a tapered waveguide.
However, Traverso, further teaches:
via a spot-size converter including a tapered waveguide (Figs. 11A & 11B; [0015], [0034], [0064], [0068], [0070] & [Claim 1]: discloses edge couplers 225 A/B that function as optical couplers and “each comprises at least one tapered waveguide configured to adjust a diameter of a mode of the first optical signal”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate via a spot-size converter including a tapered waveguide, of Traverso to Sugiyama, in order to attain and improve Sugiyama’s inspection circuit, where Sugiyama’s goal is to provide a low-labor efficient method for testing optical circuits on a wafer prior to dicing, Traverso teaches an optical coupling mechanism, an edge coupler 225 featured a tapered waveguide, whose function is to “adjust a diameter of a mode” to transfer an optical signal, teaching using tapered waveguides for efficient optical coupling and mode matching between structures, where the use of a spot-size converter (SSC) is a well-known and predictable technique in silicon photonics to reduce coupling loss and efficiently match modes between waveguides and different dimensions (such as connecting a temporary larger, testing waveguide to a dense, smaller core waveguide), a PHOSITA would recognize the benefit of using a low-loss, mode-matching SSC to replace or enhance the general coupling mechanism in Sugiyama’s testing path, improving the efficiency and accuracy of the optical inspection circuit and optimizing performance and minimizing insertion loss, by substituting Sugiyama’s general coupler with the specific SSC/tapered waveguide from Traverso, an obvious design choice to achieve the predictable results of improved coupling efficiency in the wafer testing configuration.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 March 31, 2026
/EMAN A ALKAFAWI/ Supervisory Patent Examiner, Art Unit 2858 4/3/2026